Layout XL Issue

Hi All,

I have an issue where if I turn the Layout XL to a depth of more than
one and have a pin from a subcell and I connect to that pin on the
same metal layer where there is a via under that metal pin I get the
error below. So, in the case I am seeing I have a M2 pin with Via1
below and when I connect to it I get this error. Now, I do not get
the error if I connect to the M2 with the via below moved or
deleted.

The Via is created with the Create Contact command and it is a
symbolic via. I noticed in the Layout XL Options form there is
under Verification and Generation "Properties Used to Ignore Objects"
also there is "Parameters to Ignore." I would think I could have
Layout XL "ignore" symbolic vias, but can't seem to get that to
work. Does anyone know how to do this? Why does the via have
<nil> instead of the net attached to it?

I know this seems anal, and maybe it is a little, but I have 50 or so
of this in my design.

Thank you in advance,
Eric


location: ("ukko_ga860_work" "Ukko_cur_multi_esd_sep_vdd_v4" "layout")
reason: Warning: Illegal hierarchical connection to internal net
between
instance `|I2' and path on layer `metal2 drawing' on net `<nil>'.)