Layout of Dummy MiM Capacitors

Hi,

I have questions regarding layout of MiM capacitors in for TSMC 0.25
using NCSU_CDK, with the tsmc03d design rule:

1. Do I need to layout dummy capacitors if I want good matching
between unit capacitors?

2. If I do, where should I connect the top plate of the dummy capacitors?
Is it OK to keep them floating?

3. I tried connecting the top plate of the dummies to metal 5, then down
to the bottom plate metal 4. But I get a DRC error which essentially
claims that I cannot connect metalcap to metal4. I absolutely
do not want to connect those top plates to ground. But it seems I can
only keep them floating if I follow the design rule in divaDRC of the
NCSU_CDK.

4. If I place dummy capacitors then I need to enlarge bottom plate for them.
Won't this increase parasitic capacitance of the bottom plate?
Is there a better way to layout dummy capacitors or, is there no
need to layout them?

Thanks in advance.

 

3. I tried connecting the top plate of the dummies to metal 5, then down

The error message I got is
"via4metalcap contact does not connect to two layers"

It is strange this message can't be found in divaDRC.rul.

 

Depends on who you want to fight! OK is a relative term. The fabrication of
the real
capacitors is the important thing to you.

The Clean DRC and LVS is required by the Fab! These are not the same!
The DRC and/or LVS wants to see devices connected!

Why do you care where the top plates of the dummies are connected?
especially if it is to ground? (lack of routing resource? )

Are you saying that the "dummy bottom plate" MUST be connected to the
"real" bottom plate? (This seems silly to me!)

Can you connect them both to ground (dummy bottom & Dummy top?)

Sometime the rules for MiM caps are written in ways that guarentee that they
are more immune to process induced charging, but this is often not the only
way
to handle the issue. The Fab may disagree and if you fight them here, they
tend
to wash their hands of the reliability issue.

-- Good luck!

- G

 

Aha! The famous undocumented error

The connect statement (or device recognition, or labeling ... ) required
that both
sides of a via exist. This "contact" has been improperly formed. (typically
a
loose written DRC/LVS deck that does not also explicity write a rule that
forbids the creation of illegal devices. ("illegal" w.r.t. the deck in
question).

One way that I have convinced some Fab's to allow this is the use of
deliberate
fill layers that create known inactive devices. (Not TSMC however ... )

- G

 

Thank you very much for your response!

This sounds like a good idea, but I have one concern.

The design rules say min bottom plate enclosure of top plate is 0.6um,
min spacing between two bottom plates is 1.08um. If I separate dummy bottom
plate I need to have min spacing of 2.28um between unit capacitors top
plates.
Won't this increase area and parasitics of wires connecting the unit
capacitor top plates? (since I have very small unit capacitors, 9um x 9um)