iterated instances - Mentor calls it a "Frame"

I'd like to create a schematic box (in Mentor ICstation it's called a
frame) or subcell that netlists with iterated instance names - and
iterated parameter values. I can place identical elements in a Cadence
schematic, for example a 1k resistor, R1:40. But what I really want is
to have a resistor ladder with resistors along the chain dropping in
value with instance name and the resistors to ground rising in value.
It's really ugly on a schematic, and it doesn't deserve more scrutiny
than the rest of the circuit, which now looks smaller, gets.
Before I sign up for a Cadence consulting agreement, I'd like to know
1 Has anyone done it?
2 How much work was it?
3 which part of the netlisting process is the worst?

Steve Schwarzbek
[no, i don't need any "X4n4x"]

 

For the topology, that should be doable. Most people use iterated
instances to do parallel connects, but it is in fact rather easy to do a
series connect:
instance R<1:11> , label the bus on the top pin "first,ni<1:10>" , label
the bus on the bottom pin "ni<1:10>,last". Voila.

For the values, you might need to do stg more ugly, like use the
instance name as part of an AEL expression.

You can maybe do it better at the netlist level, make a subckt
definition of yours.