Is it possible to connect two layout instance by SKILL?

Hi,

I want to know if it's possible to connect two instances for pCells
from specific library in layout view with SKILL code?

I don't want to give as anything to the SKILL rather than the name of
those two instances, and it should be able (through other PDK contents
or tech file or whatever) determine the layer which is suitable for
connectivity, and do draw the connecting shape (path, polygon, or
whatever).

I think that obtaining the lpp of each pin layer of the two instances
is a clue for doing that.

What do you think?

Thanks and best regards,
Ahmad

 

Hi Ahmad,

I don't really understand the question. Are you trying to write your
own automatic router ?
Well I'm afraid it wont go any further with the very restricted
amount of information you want to feed it with.
Perhaps I'm misunderstanding your query. Would you mind to make it
clearer ? An example of what you are aiming for is much appreciated.

Regards,
Riad.

 

Hi Ahmad,

I don't really understand the question. Are you trying to write your
own automatic router ?
Well I'm afraid it wont go any further with the very restricted
amount of information you want to feed it with.
Perhaps I'm misunderstanding your query. Would you mind to make it
clearer ? An example of what you are aiming for is much appreciated.


Regards,
Riad.

 

Hi,

I was about to reply the same.
Using a router seems to be the best solution (ccar, vcar, vsr,
encounter? ...)

Otherwise, if the pins to connect are "face to face" and so the
connection is a straight path without any angles, it is possible to do
what you want relatively easily with XL.
Getting the pins shapes and geometry (to know the width of the path
and the metal to start) and the associated nets, and then draw the
pathes.
But writing that I remember that XL provides a way to automatically
complete a net when you've started to draw it.
Maybe this can scripted and allow to draw more complex nets (not only
managing net interesections if pins are not face to face, but layer
changes if a pin is in metal1 and the other in metal3 for example) .

Finally, go back to Riad's question : Why not using a router ?

Sylvain

 

Hi Riad and Sylvain,

Thanks for your advices.. It's nice to hear about the router! I don't
know that there's SKILL built-in commands for routing (if I understood
correctly)..

Riad,

What I really want to do is a simple test pattern generation. Which
will have instances of devices pCells in an array in the layout sheet,
and I want to automatically connect their pins one time serially,
another parallel, and other times randomly (or pseudo intended
random).

I guess this can be done with connection layer paths with maximum two
bends per path, since the placement is flexible and we've not obey any
layout optimization or DRC rules at this point.

Sylvain,

Since I've never heard before about these routhers, I looked for ccar
in sklayoutref, and I found some functions that invoke router, when I
tried one (iccStartCCAR) I got a message saying: "Cannot find Router.
Current path is: vcar, would you like to select a different path?"
What does that mean?

And what about XL commands you have pointed to? Can you please give
some additional clarification?


Thanks and best regards,
Ahmad

 

Hi Ahmad,

I still don't see the point of having to connect your Pcells for that
test Pattern !
In fact, what is your test pattern is aimed for ? Validate a process ?
prove DRC/LVS clean ? ....

Traditionally, process validation is done using inverter chains.
That's for all the reasons I wouldn't detail in here.
If you want to prove LVS, then it is better to generate individual
cellViews for each pcell combination, stick few pins on it and here
you go.
Simple things are more efficient and easier to develop, maintain and
debug.

Again, the question you need to answer is : What Am I going to use my
test pattern for ?
My experience is most of the test patterns don't need the
connectivity.

The only times I have had to route my blocks, I did go for a router as
Sylvain advised. It was faster for me than developing my own scripts.
I was likely to spend months writing 'an average' script ...

Cheers,
Riad.

 

Hi Riad,

Thank you very much for your advice. Actually my aim, as you guessed,
is to develop an LVS testing through series of checks (series
reduction, parallel reduction, connectivity recognition, circuit
recognition, ...).

I was thinking of obtaining an almost close emulation of the real
world cases. Why do u think I don't need connectivity in my TPs? And
in case I will need to connect them out, where to get more info about
available routers?

Moreover, don't you think that ROD functions could be used for direct
pin-to-pin routing as it's almost the case for me?

Thanks,
Ahmad

 

Ahmad wrote, on 08/05/09 13:05:

If the connections are relatively straightforward, and the pin objects within
your cells have ROD handles, it would be easy to create a path from I1/pinA to
I2/pinB (assuming there's a handle called pinA and pinB).

It's very hard to give generic advice for this, because a generic solution would
essentially be a router - and that's not something you're going to want to have
to write from scratch! In many cases you can make simplifications, but exactly
what those simplifications are is hard to tell without seeing the cells
themselves and exactly what you're trying to do.

For the router route (excuse the pun), if you're using IC5141, you'll need to
install ICC11241 to get access to VCAR (Virtuoso Chip Assembly Router). In IC61X
it's included as part of the stream (there's also VSR - Virtuoso Space-based
Router in IC612 onwards). Docs are of course in the installations.

Best Regards,

Andrew.