Importing DEF file in Cadence DFII

Hi everyone,
I created a layout in SOC encounter and I saved it as DEF.
Then I import it in Cadence and open it using Virtuoso. When I run DRC
I don't get any errors but when I extract the layout (divaEXT) I get
the following error:
"Figure Having No Stamped Connections"

A huge "X" appears around the entire layout. Can someone explain this
error and how can this be removed? BTW, I am only selecting
"special-nets" while importing the DEF in DFII (so I have only VDD and
GND nets in the imported layout).

thanks
Trisha

 

Your extract flow is probably using something like:

geomStamp(psub ptap error)

to do substrate connectivity. Diva is telling you that you
don't have any substrate taps in your DEF-import layout,
so psub is floating.

If that doesn't matter to you, you can just ignore the
warning.

If that does matter to you, you need to stick at least
one substrate tap somewhere in the layout, connected
to your ground (presumably).

-Jay-

 

To add to this.

It may be that your deck has specific switches that allow substrate
connectivity ...
It looks like they may be off.

Or a bug in the deck.

Or you have multiple nets connected to the substrate ( i.e. vss! , vee! or
vss1! , vss2! or a digital and an analog ground .... )

Several fab decks have creative (not good ) ways of getting around this.
My favorite is the "magic ring" that breaks the substrate net into different
electrical nets.
All you do is draw a polygon on this layer around each substrate domain ....
( then the error goes away, but the problem ... )

 

Thanks for help.

Trisha

 

I have no problem when people mislead the tool to get a clean result.

I do have a major problem when people do not understand the problems that
this causes.

My method for dealing with this was to introduce the "substrate aware"
verification methodology
which I think was a more accurate model.

The substrate rings or areas are a fiction that lets you mess up multiple
supplies and still get a clean lvs.

(unless they are sufficiently separated by substrate impedance ... ;^) )

YMMV

 

Partitions will hide softconnects, but they will show metal connection
between two substrate domains. And the latter is a very insteresting
feature when you want to avoid that you cmos bulk net directly
contaminates the RF substrate net.

What does the "substrate aware verification methodology" look like ?

 

The "Substrate Methodology" is one in which the substrate is a conductor
that
only connects to "substrate" devices. The layer is the size of the cct being
extracted.

I proposed that this device netlist out as a 1 ohm resistor.

For example:
A chip has 3 sets of supplies ... lets call them VDD3!, VSS3!, VDD1!,
VSS1!, VCC!, VEE!
which are for power and ground in the 3 volt digital, 1 volt digital, and
3.3 volt analog domains.

I am constantly told by people that they want to verify that the VSS<n> and
VEE nets are not "connected".
I understand why! Although the substrate is relatively resistive, all of
these signals (when connected by tie-down devices
to the substrate ) are required to be the same (DC) potential! (or large
un-allowed substrate current would result!)

But we all know that if we logically short the negative supply nets in LVS,
then we cannot detect the shorts. ( at least in the schematic side!)

I think that the soft-connect solution is not clear or well thought out, so
I propose we replace these with a tiedown device.

( in my system, the chip in the examples has 4 negative supply nets, the 3
listed and a global gnd! net. Each tiedown device has
it's P+diff connected to the net that the supply brings from the contact to
the metal and the substrate half is gnd!

Note that in this system, all devices that have implicit connections to the
substrate ( i.e. the bulk node of mosfets outside pwells or
the substrate node of parasitics from conductors to the substrate ) must
connect to the gnd net.

Now the layout and schematic both have the same view of power nets AND we
can run lvs.

--- Gerry

( This is messy to do in practice, if you don't like messing with PDK guts
.... )

 

Gerry,

agree. This is cleaner. How much messing around with the extraction
decks and the PDK is involved ?