IES81, OVM 2.0, and Systemverilog parameterized class definitions?

Discussion in 'Cadence' started by guestuser1, Nov 9, 2008.

  1. guestuser1

    guestuser1 Guest

    In the OVM2.0 user-guide, they go through some general object-oriented
    programming concepts (classes, etc.)

    This includes examples with parameterized SV classes:

    class my_widget #( parameter int DATA_WIDTH = 32 );
    ....
    endclass : my_widget

    typedef struct {
    ...
    } ts_blah;

    class my_super_widget #( parameter type T = ts_blah );
    ....
    endclass : my_super_widget

    I tried this isolated class-declaration inside Modelsim XE 6.3c, and it
    compiled and simulated without problem.
    (of course, XE won't do OVM at all.)

    But when I tried to compile this in IES81-s006, irun returned a
    compile-error.
    Apparently, parameterized systemverilog classes are not supported yet.

    Am I missing something? Is the OVM 2.0 user's guide just giving abstract
    examples that may or may not work on existing OVM-compliant simulators?
     
    guestuser1, Nov 9, 2008
    #1
  2. guestuser1

    Amal Guest

    You can do OVM on SE as well, as long as you have SystemVerilog
    license. I suppose you can even run it on PE if you have
    SystemVerilog license. OVM is pure SystemVerilog class library. For
    constrained random, functional coverage manager, and other features
    you need questa.

    -- Amal
     
    Amal, Nov 10, 2008
    #2
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