how to use switch-RC in verilog-XL in cadence

Discussion in 'Cadence' started by harry, Jul 28, 2004.

  1. harry

    harry Guest

    Hi
    I was trying to use switch-RC of verilog XL.I didn't find any good
    tutorial on the web for using it effectively to do switch level
    simulation on large designs.
    I open Verilog-XL option from my composer window.IN the netlisting
    option I chose switch-RC option.And i run the simulation .The assigned
    switch-RC parameters like driveStrength,TF ,tr ,doesn't seem to have
    any difference in the output waveform.I use simvision to view
    waveforms.
    Secondly I have read on the groups that ,Switch-Rc is 80-90% close to
    spice.
    Only thing I have been able to do with it is see logic simulation and
    strength of my nets as weak,medium or strong.
    Can it provide me rise and fall time of nets ,or do design
    verification for path delays and timing optimizations.
    I am messimg with this stuff for over a month now ,doesn't seem to get
    anywhere,
    If anybody has a clue ,please help me out,.

    regards
    Harry
    portland state university
     
    harry, Jul 28, 2004
    #1
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