how to use "adc_dnl_8bit" for DNL simulation?

I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

 

Did you read the comments at the top of the Verilog-A code? (in the veriloga
view of this cell in ahdlLib). It seemed reasonably clear to me..

Broadly speaking, this block generates the clock pulse and voltage input for
the ADC under test, and then the output of the ADC is fed back into the
adc_dnl_8bit block. It sweeps the input voltage level, does a number of
conversions, and uses the results to calculate DNL.
Various parameters control the voltage levels, timing etc.

Regards,

Andrew.

 

Dear Andrew (and others),

Thank you so much for your quick reply!! Since I'm fairly new to this,
I still have a few things which are not clear.

1. You mentioned "this block generates the clock pulse and voltage
input for
the ADC under test". But I remembered in the adc_dnl_8bit block, vout
is the only output, and vclk is supposed to be an input terminal, how
could we feed these two into the ADC under test?

2. What I was doing is, I use a ramp source as the input for the
ADC_under_test, whose outputs go into adc_dnl_8bit block, and I use a
clock source to feed into the both blocks (ADC_under_test and
adc_dnl_8bit block), but I keep getting error: the net29 (i.e., vclk of
adc_dnl_8bit block) forms a rigid loop (shorts) when added to circuit
(Vclk: 0). Could you advise what's wrong here?

3. What exactly is the output of adc_dnl_8bit block? How can we get the
DNL plot directly out of it?

Many thanks! Your help will save me days of time, so I really
appreciate your previous time!

 

No, vclk is an output as well. The model itself doesn't actually define pin
directions, but if you look in the code, there's a contribution for the vclk
output:

V(vclk) <+ transition(vclk_val,0,30u,30u);

Ah, I see the problem. The pin on the symbol is an input pin. Well, it
shouldn't be, and that's a bug. I'll file a PCR for that.

So, connect it up as if it were an output, and ignore the schematic
checker warning about you having a floating net.

If you're really worried, take a copy of the cell and change the pin direction
on the symbol of the vclk pin.

Well, this is because the V(vclk) contribution above is a voltage source, and
you're shorting it out with another voltage source. Which isn't allowed (not
without lots of sparks!).

It doesn't plot DNL - but prints it out. Look in the code, it's pretty
obvious!

 

I filed PCR 802181 to get this pin direction corrected.

Andrew.

 

What is adc_dnl_8bit?
Is it IP that Cadence do provide?
Or is it IEEE IP?
Or what?

 

Thank you, Andrew!

After played around it for a while, I think I'm getting close there.
Here is another question.

Regardless how I change the values in the CDF form of the blocks, the
values actually never change. I have to go into the source file to edit
them. Could this be a bug?

Also, where's the default location for the log file? Is input.dat under
netlist/ the correct result file?

Many thanks!!!

 

Why are you changing values on the CDF form? (I assume you mean the
Tools->CDF->Edit CDF form) - this is primarily set up to reflect the
parameters in the Verilog-A model, so that there's a placeholder for create
instance and edit properties. The actual default values are held in the
Verilog-A code.

What you would normally do is set the properties on the _instance_ by doing an
edit properties on the instance of adc_dnl_8bit and set them to the values you
want. That should work (I've not tried it, as I'm not in the office at the
moment, but I can't see why it wouldn't work).

Regards,

Andrew.

 

If you'd read the previous postings, you'd see that it is a sample verilog-a
model provided in the ahdlLib library, in:

<ICinstDir>/tools/dfII/samples/artist/ahdlLib

and is a block for characterising the DNL of an 8 bit ADC. Read the comments
in the Verilog-A code for more detail.

Regards,

Andrew.

 

Thank you, Andrew! Is input.dat the output file which contains the
DNL's for all the codes?

 

Yes, looking at the code, if log_to_file is set to non-zero, it writes to a
file called "%C:r.dat" - this means the input file name, stripped of its
suffix, with .dat appended. If the input file is input.scs (which it is from
within ADE), the output file will be called input.dat.

The code mentions a parameter "filename" - but that is not implemented in the
Verilog-A version of the code - it was there in the spectreHDL code. string
parameters were only recently added to Verilog-A, but this model predates
that.

Regards,

Andrew.