How to simulate PLL phase noise efficiently

Discussion in 'Cadence' started by Gang Bu, Jan 9, 2007.

  1. Gang Bu

    Gang Bu Guest

    Hi, all:

    I am working on a 24 GHz PLL with loop bandwith of 0.5MHz. Does anyone have
    any segguestion on how to simulate the overall closed-loop phase noise
    (postlayout) efficiently? I guess this is a well known problem. It seems to
    me that I need a huge hard disk, as well as several days of waiting.
    Appreciate your help.

    Best regards,
    Gang
     
    Gang Bu, Jan 9, 2007
    #1
  2. Gang Bu

    Andrew Beckett Guest

    A good place to look is:

    http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

    Andrew.
     
    Andrew Beckett, Jan 12, 2007
    #2
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