how to run VHDL-AMS Simulation in Cadence

Hi,

I would like to simulate a schematic/layout generated in Cadence using
VHDL-AMS models. How do I set this up using IC5.0/LDV5.0 and how do I
run simulations?

Also, how can I run the simulations from the command line as in
Spectre or VerilogAMS?

Thanks in advance,
Peter Wilson

 

Have you read the documentation on AMS Designer?

There is a tutorial included as well (may not use VHDL-AMS, but Verilog-AMS, but
you should be able to get the point).

Andrew.

 

Yes, I have read the docs, obviously they are aimed at Verilog-A(MS),
but there is no detail for VHDL-AMS.

I can see the general principles, but getting , for example, the -AMS
option in ncvhdl is not clear in either the documentation or the GUI
(it works fine at the command line).

All I need now is an example of how to set up a resistor, say, and
then netlist a schematic containing VHDL-AMS elements targetted to
ncvhdl, with the AMS options. Then I can extend this to pretty much
any block. I have figured out the simulator (including options) and
SimVision, so getting the netlister working would be brilliant.

Thanks,
Peter

 

Peter,

Apologies for the delay in responding to this.

You can created VHDL-AMS textual views in DFII by using File->New->CellView
and selecting "VHDLAMS-Editor" as the tool. Any view created this way will be
compiled using ncvhdl with the -ams option.

However, with AMS Designer, schematics are always netlisted as Verilog-AMS,
and not as VHDL-AMS. This was a conscious decision, for a few main reasons:

1. Verilog-AMS allows automatic insertion of connectmodules when disparate
disciplines are connected to each other; VHDL-AMS doesn't allow this, and
so by netlisting schematics in Verilog-AMS you get more flexibility.
Because VHDL is strongly typed, the types of signals connected together
have to match, whereas Verilog-AMS's connectmodules allow you to
automatically convert one type to another.
2. The simulator supports mixed-language, so there's no real benefit in it
netlisting to VHDL-AMS.
3. It would require another netlister to be written, and since there were no
compelling reasons to have the netlist in VHDL-AMS, that hasn't been done
yet (I guess this third point is a little tautological).

So practically it all works together, but if you're using VHDL-AMS for religious
reasons (choice of VHDL or Verilog is often a religious thing rather than for
any particular language capability), then this lack of rigour may disturb
you ;-)

Andrew.