how to perform gate-level simulation with verilog-XL

Hi.

I've just finished RTL simulation with verilog-XL and want to know how
to run gate-level simulation with verilog-XL in a non-gui fashion.

Below is how I used verilog-XL command to do the RTL simulation.

("sim.f contains path information of all relevant *.v files)

Is there anyway that is similar to this to do the gate-level
simulation?
Thanks in advance.

-Seungwhun

 

For gate level netlist, you can try fast SPICE tools such as UltraSim
to simulate it.

Regards,
Yuchun

Ledi 写é“：

 

It's exactly the same. Verilog-XL (or indeed any Verilog simulator) can simulate
gate-level descriptions just as easily as RTL.

Presuming you've synthesized the RTL (either with a tool, or by hand!), just
give the gate level netlists to the simulator, with the testbench that you used
with the RTL.

I'm a bit surprised you're asking this, because it's kind of a basic question.
So I wonder whether you're actually trying to ask a different question than you
actually asked?

Regards,

Andrew.