how to measure power dissipated in a digital circuit

I was reading a paper on "LOW-POWER DIGIT-SERIAL MULTIPLIER"
And I came accross a problem of how they measured the power dissipated
in the Multiplier which they have designed.
It said on a paper that,they are using HEAT:Hierarchical Energy
Analysis
Tool,which is based on SPICE.
I discussed with my Prof about this,but he adviced me not to use a
HSPICE
(which is available in our Uni) because a Multiplier is too big a
circuit
to use HSPICE.
My question is how to Am I going to measure power dissipated in a
digital circuit(in this case a Multiplier)

Thanks in advance,
Chris

 

How big?

Typically you would run a HSPICE/SPECTRE simulation of the smallest path
through the multiplier.
or through each of the building blocks.

Then you would obtain an understanding of the relationship between input pin
activity and power consumed.
(assuming all edges are settled and well behaved)

Then you simply codify the input stimulus you have and measure the power
produced by each input vector
transition. (Simple to say, very complex to actually do!)

Note that most large circuit power estimation tools work on standby leakage
for static lines and
some fixed amount of power for a know toggle.

Note that the input space for a multiplier can be quite large. It might be
tricky to isolate which transitions
would take the most power.
(my guess would be the transition that causes the most nodes to flip OR the
transition that activates the
longest ripple in the longest path ... and this would be implementation
dependant!)

Hope I have not confused the issue.

Good luck.
-Gerry