how to make Verilog netlist without a Verilog license

Discussion in 'Cadence' started by DReynolds, Jun 21, 2006.

  1. DReynolds

    DReynolds Guest

    I am working on a mixed signal chip and I would like to create a
    Verilog netlist of some of my blocks for the digital guy on the
    project. I am using DFII and I do not have a NC Verilog license, do I
    need on just to create a netlist? I tried Tools->Simulation->NCVerilog
    from the schematic and File->export from icfb with no luck.

    If I can't make a netlist directly, does anyone have a spectreToVerilog
    ((or CDLToVerilog) converter they can point me to? A quick search of
    this site did not turn up anything....

    thanks in advance

    DAvid Reynolds
     
    DReynolds, Jun 21, 2006
    #1
  2. You do not need a Verilog license or NC Verilog license to netlist.

    You do however need a "21400" license (" Virtuoso(R) Schematic Editor Verilog(R)
    Interface").

    In other words, you don't need a simulator license to do this, just an interface
    license.

    Regards,

    Andrew.
     
    Andrew Beckett, Aug 2, 2006
    #2
  3. DReynolds

    DReynolds Guest

    Andrew, thanks for the reply. Unfortunately, the fact that we needed a
    special product just to make the netlist was not known when we decided
    our mix, so we have to do without. Since I was just netlisting a few
    blocks and not a huge design, I just wrote a spectre to verilog netlist
    translator in skill. It wasn't too bad .... just a speedbump along the
    way.

    The question of should Cadence market netlisters to Verilog as a
    separate product like they used to do for Hspice (everyone raise your
    hand if you had a cdl-hspice or spectre-hspice translator skill program
    from your CAD group back in the day) I will leave to a different
    thread...


    David
     
    DReynolds, Aug 3, 2006
    #3
  4. DReynolds

    jayl-news Guest

    David,

    No special license is needed for basic Verilog netlisting.

    Once you've got appropriate appropriate verilog stopping
    views set up, and you want to netlist your dfII schematic
    "block1" in library "lib1", just:

    simInitEnvWithArgs("/tmp/block1_net" "lib1"
    "block1" "schematic" "verilog" t)
    simRunNetAndSimWithArgs("lib1"
    "block1" "schematic" "verilog" t nil nil 10)
    Tools->Simulation->Other
    Simulation->Initialize...
    /tmp/block1_net
    other->verilog
    Simulation->Netlist/Simulate
    Run Actions=netlist (turn simulate off)

    Works great. -Jay-
     
    jayl-news, Aug 3, 2006
    #4
  5. DReynolds

    DReynolds Guest

    Jay, thanks for the info... I will give it a try.


    David
     
    DReynolds, Aug 4, 2006
    #5
  6. Jay,

    You're quite right. I forgot about this.

    The license is needed to interface to the simulator, rather than just produce a
    netlist.

    Andrew.
     
    Andrew Beckett, Aug 4, 2006
    #6
  7. DReynolds

    DReynolds Guest

    Jay, I tried it and it seems to work... thanks! The only problem is it
    is not doing explicit netlisting and I can't seem to find it on the
    options... how do I set it for explicit netlisting?


    thanx

    David
     
    DReynolds, Aug 8, 2006
    #7
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