How to locate a floating gate in layout

Hi everyone,
Is there any way to check if the transistor terminals unconnected in
layout.

For example:
In a block level the inverter gate is not connected in schematic and
so the layout has been done accordingly.
Now I want to search in my topcell which are those transistors which
donot connect.
LVS wouldnt catch because the schematic also doesnt have a connection.
DRC throws error only if the gate of a transistor doesnt have a
contact, otherwise if there is a contact on gate and if that is not
connected the DRC doesnt catch it.

Can you guys please help me to write a SKILL code to catch the
unconnected transistor terminals.
Thanks in advance,
Subhash

 

I found that the "filter" option in avcompareRules (in LVS form) does
this.

I tried this option but not able to see the results.
Please suggest..


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Do up have Assura? Assura will flag this regardless of the
connectivity in the schematic with ERC in 3.17 and above.
Check the ERC section and it should look something like this

ercPathCheck( noLabeledNets and noPwr and noGnd gateNetsOnly
ignoreUnused "This is a floating gate")

There might some additional hooks required

Rick