How to estimate the size of the chip from the netlist?

Discussion in 'Cadence' started by yuama215, Apr 13, 2009.

  1. yuama215

    yuama215 Guest

    Hi,
    Everybody,who can tell me the example program about skill?
    The size of the chip can be estimated from the netlist with this skill
    program,pls help me
    Thank you!
     
    yuama215, Apr 13, 2009
    #1
  2. yuama215

    Riad KACED Guest

    Hi There,

    Really a hard script to write even though some people from the
    marketing departments find it easy to write Excel macros that does the
    job. I have never been convinced ...
    What you could start with is:
    1. Collect your devices from the netlist. Calculate the total area
    assuming you know their geometries. I assume your netlist does contain
    the W/L information for your MOS, RES, CAP, Diodes, BIP, IND ... etc.
    This is not quite accurate since you might be able to stack some
    devices under the caps, leave some guard spaces around the
    inductors ... etc. In other words, a simple addition is not 100%
    accurate.
    2. Get the area information for all your standard cells, i.e : Logic
    gates, memories, IOs ... etc used in your design
    3. Estimate the area taken by the routing. This is the complicated
    bit, it depends on the number of layers you are using to route, the
    topology ... etc. This might be a certain percentage of the area of
    the devices, say 20% as an example.

    In a real world, area estimation is often based on past experiences.

    These are few ideas to resolve a rather not-so-easy question.
    You might ask the marketing people around you, I always felt like they
    had magic equations for this question !

    regards,
    Riad.
     
    Riad KACED, Apr 13, 2009
    #2
  3. yuama215

    yuama215 Guest

    Thank you for your answer!
     
    yuama215, Apr 14, 2009
    #3
  4. yuama215

    Riad KACED Guest

    Riad KACED, Apr 14, 2009
    #4
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