How to convert VHDL/ verilog code to layout?

Hi, All:

Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout.

Thanks a lot!

Boki.

 

You're asking a very basic question.
The simple answer is "place and route".

If your netlist is not gate netlist, synthesized it into gate netlist.
Basic steps:
1. make a floorplan for your design. Just make a simple one.
2. place your standard library cells (represent the gates in the netlist).
3. route the gates. Silicon Ensemble could address these three steps.
4. get the result (DEF) into Opus layout or gds file (streamin into Opus layout).

thanks,
ronald

 

-the cadence product is called PKS. There is also stg called buildgates
but I find it sound terrible.
-the activity is called synthesis.

All good books at the nearest grocery store. All good software at your
closest butcher: cadence, mentor graphics, xilinx (in alphabetical order).

Your questions is (... how to say it ...) off topic.

So, you were you given all those expensive cadence licenses to play with
while you don t know that... Please tell me who your employer is !

 

I got it, thank you very much!

Boki.

 

A quick search shows the SAME question posted (separately) by BOKI to:
sci.electronics.basics
sci.electronics.cad
comp.cad.cadence

This same pattern of posting the SAME posting SEPARATELY to multiple
newsgroups is repeated, time and time again, by BOKI, e.g.:
sci.electronics.design SUBJECT: Why Sigma-Delta modulator?
sci.electronics.basics SUBJECT: Why Sigma-Delta modulator?

The repeat questions to multiple groups seem to be cut and pasted.
Mostly it's analog stuff (besides the personal stuff) that BOKI posts.
Yet, even Calibre questions are posted to comp.cad.cadence:
comp.cad.cadence
sci.electronics.cad
Again, both with the SAME subject line:
SUBJECT: Calibre Error: Enviroment variable MGC_HOME is not set

Many posts by BOKI are in an Asian font (I suspect Chinese), e.g.:
Subject: 離台北火車站400公尺
16F套 房出租
Newsgroups: tw.bbs.forsale.house

Some posts by BOKI seem to trend somewhat like this one:
From: boki ()
Subject: need 1ns three input nand gate example
Newsgroups: comp.lang.vhdl
Date: 2003-03-02 10:39:01 PST

Could you give me some example for these:
(1) 1ns three input NAND gate
(2) 1ns XOR
I am new to VHDL.
Thanks.
Boki.

Message 2 in thread
From: Theron Hicks (Terry) ()
Subject: Re: need 1ns three input nand gate example
Newsgroups: comp.lang.vhdl
Date: 2003-03-02 19:05:05 PST

Boki,
Get a clue! DO YOUR OWN HOMEWORK!!!!! Who is the proffessor for
your class? Can you give me his E-Mail? No!!
Then no homework answers in this newsgroup!!
Theron

Everything stated here is a matter of public record.
Polly

 

Polly,
Don't you have anything better to do with your time? If you don't like
Boki's postings then just don't read them.

Frank

 

So? What's the problem with you? Any question?
I am not IC design student before, I learn it by myself, can't I?

If any question, please Email me, or don't waste any public resource,
thank you very much.

Boki.