Hierarchical place and route with Encounter (power routing to blocks)

Hi -

I'm trying to figure out how to place and route a hierarchy with SOC
Encounter (v5.2). I must be missing something because it shouldn't be
this hard! What I've done is:

1 - Start by place and routing a core macro. This works fine. I have a
vdd! and gnd! ring around the circuit. I generate DEF and Verilog and
read this back in to dfII and it DRC's and LVS's just fine. I'd like to
use this macro in another design as a pre-designed macro!

2 - In SOC I use lefOut with the -stripePin option to get a lef file
with vdd! and gnd! pins. I also generate a .lib file using
do_extract_model. (I've also tried generating the lef file by running
abstract on the layout view from dfII - same behavior)

3 - In SOC in my top-level design I import the core.lef and core.lib
files in addition to the other stuff for my top-level design. The core
is instantiated in my structural verilog file. When this is imported I
get a core block that I can place in the floorplan.

4 - I can pick up and place the block, put a halo around it, etc. All
seems fine...

5 - HERE'S THE PROBLEM - when I do my power planning (rings and
stripes), I can NOT get the power routing connected to this macro! I've
tried with the macro as CLASS BLOCK in the lef, I've tried with the
macro as CLASS RING in the lef. I've tried making the vdd! and gnd!
ports also of CLASS RING. I've made sure that I'm selecting the block
pins in sroute. I've even followed the convoluted power planning
template flow in the dtmf tutorial included with SOC.

NOTHING WORKS. The power routing ends up connected to the pads,
connected to the standard cell rows, and the stripes are connected to
the standard cells rows. But, the stripes just end before they get to
my core macro. They don't connect to it!

It seems as if the nanorouting for the signal pins also works fine.
But, I can't get SOC to connect the vdd! and gnd! wires to my macro.
This macro was placed and routed by SOC, and the lef and lib were also
generated by SOC. It must be possible to use it in SOC!

Help! What am I doing wrong or what am I not doing that needs to be
done to make this work?

Thanks!
-Erik

 

Are you vdd/vss pins marked with "use power", "use ground" ? Also make
sure that their names match the power, ground net names you define in
your design configuration.

 

Good thoughts, but yep - they are marked with USE POWER and USE GROUND,
and they have the same names (vdd! and gnd!) as all the other power
supply pins in my library...
The LEF file was generated by SOC using lefOut so I have to hope that
it generated reasonable LEF for reading back in to SOC, but I've been
wrong about that sort of thing before! :-(

-Erik

Here are some excerpts from the SOC-generated LEF. The original had
CLASS BLOCK, and no SHAPE statement in the vdd pin's port. That didn't
work so I tried modifying things to be CLASS RING. Still no luck...
Ideally I don't want all the stripes extracted separately. The macro
has been placed and routed with vdd! and gnd! rings so all that really
needs to be in the LEF is the outer rings, but there seems to be no
option to lefOut to do that. Without the
-stripePin option the SOC-produced LEF has no vdd! and gnd! pins at
all.

MACRO controller
CLASS RING ;
SIZE 268.5000 BY 249.0000 ;
FOREIGN controller 0 0 ;
ORIGIN 0 0 ;
SYMMETRY X Y R90 ;
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER metal2 ;
RECT 149.5500 0.0000 150.4500 0.9000 ;
END
END clk
....
# P/G power strip data as pin
PIN gnd!
DIRECTION INOUT ;
USE GROUND ;
SHAPE RING ;
PORT
LAYER metal1 ;
RECT 16.5000 55.8000 31.2000 58.2000 ;
END
PORT
LAYER metal1 ;
RECT 16.5000 109.8000 31.2000 112.2000 ;
END
....

END controller

 

One other question would be the SITE attribute of your LEF. Do you
have one ? If so, what is its CLASS ? Try putting a CLASS BLOCK to
your MACRO and a CLASS CORE to your SITE sections.