Help needed: Extract with NCSU_CDK.1.4 in Linux Fedora 3

Discussion in 'Cadence' started by Liang-Kai Wang, Apr 2, 2005.

  1. Hi,

    I installed NCSU_CDK 1.4 in Fedora 3.0. I use IC 5.0.33. When I do
    extract on my Layout, I see the following error message. Does this
    mean I didn't install NCSU library correctly? Can NCSU 1.4 work with
    Fedora 3.0 and IC 5.0.33?

    thanks,
    Liang-Kai
    ================
    \o library: cla64
    \o cell: cla64
    \o view: layout
    \o Rules come from library NCSU_TechLib_ami06.
    \o Rules path is divaEXT.rul.
    \o Inclusion limit is set to 1000.
    \o Switches used: Extract_parasitic_caps.
    \o Parsing drcExtractRules of
    "/crystal/eda/cadence/local/lib/NCSU_TechLib_ami06
    /divaEXT.rul"...
    \o error: Invalid input for multiLevelParasitic(); a cap list is
    expected.
    \o error: Illegal input layer capacitance found in saveParasitic().
    \o error: The number of entries of property list and layer list must
    be the sam
    e.
    \o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
    NCSU_Analog_Parts")
    \o error: Invalid input for multiLevelParasitic(); a cap list is
    expected.
    \o error: Illegal input layer capacitance found in saveParasitic().
    \o error: The number of entries of property list and layer list must
    be the sam
    e.
    \o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
    NCSU_Analog_Parts")
    \o error: Invalid input for multiLevelParasitic(); a cap list is
    expected.
    \o error: Illegal input layer capacitance found in saveParasitic().
    \o error: The number of entries of property list and layer list must
    be the sam
    e.
    \o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
    NCSU_Analog_
    Parts")
    \o error: Invalid input for multiLevelParasitic(); a cap list is
    expected.
    \o error: Illegal input layer capacitance found in saveParasitic().
    \o error: The number of entries of property list and layer list must
    be the sam
    e.
    \o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
    NCSU_Analog_
    Parts")
    \o info: If short location check is desired later on, check the
    saveInterconnect
    \o statement for correctness:
    \o Interconnect layer nwell, pwell, pBulk not saved.
    \o Interconnect layers merged on save: elecHighres, elecRes, polyRes,
    nwellRes.
    \o Interconnect layers merged on save: cp, pDiffContact,
    nDiffContact, pOhmicCo
    ntact, nOhmicContact, ce.
    \o Interconnect layers merged on save: pDiff, nDiff, pOhmic, nOhmic.
    \o
    \o Errors exist in the rules file
    "/crystal/eda/cadence/local/lib/NCSU_TechLib_a
    mi06/divaEXT.rul".
    \o Verification program terminated.
    \r t
    \r t
     
    Liang-Kai Wang, Apr 2, 2005
    #1
  2. On Mon, 24 Oct 2005 03:10:09 -0500,
    I took a look at the divaMultiLevel.il you posted to chiptalk and was
    able to reproduce the error mentioned in the discussion, by forgetting
    to run all the layers through geomConnect. Did you have something after
    the "Errors exist in the rules file" line? It might direct you to the
    source of the failure.

    On a side note, I noticed that there are two cap clauses for the same
    layer pair, using the same parameters. This will double the capacitance.

    Parsing drcExtractRules of
    "/usr2/ekalenda/pcrdata/example/Lib/divaEXT.rul"...
    error: Illegal input layer capacitance found in saveParasitic().
    error: The number of entries of property list and layer list must be
    the same.
    saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor symbol
    analogLib")
    Errors exist in the rules file
    "/usr2/ekalenda/pcrdata/example/Lib/divaEXT.rul".
    *WARNING* multiLevelParasitic() - This cannot be used before the
    'geomConnect' command.
    Verification program terminated.


    Ed "Mr. Diva" Kalenda
     
    Edward J Kalenda, Oct 24, 2005
    #2
  3. Thanks for the test case. I was able to find the problem and adjust the
    rules compiler to handle it.

    Every coefficient is zero for elec to metal2. The rule compiler was
    changed to skip the processing steps with a coefficient of zero since
    they won't produce anything and was skipping them all. This caused the
    message about an invalid multiLevelParasitic rule.

    The techfile for the PDK should be corrected to have meaningful values,
    but that's up to the NCSU people.

    The rule deck is also odd in that it has duplicate cap clauses for elec
    to metal2, and for elec to metal1.

    Ed "Mr. Diva" Kalenda
    Cadence Design Systems

    This is just me blathering, not the company, since they don't let talk for them.
     
    Ed Mr. Diva Kalenda, Nov 9, 2005
    #3
  4. Hi Ed,

    thanks so much for fixing this Diva problem.

    I posted a patch to the NCSU PDK 1.4 here:
    http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=53

    To summarize, Ed fixed 2 bugs in the NCSU PDK:
    - Syntax error in divaDRC.rul
    - Diva Extraction fails under IC51-41

    Patches for both bugs are provided at the above website.

    Thanks again,
    Johannes Grad
     
    Johannes Grad, Nov 10, 2005
    #4
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