generic schematic gates and layout

Discussion in 'Cadence' started by rick, Aug 6, 2009.

  1. rick

    rick Guest

    Im working at a place that will instantiate generic logic gates from a
    reference library and the L/W is inherited or pushed down to the
    devices which works at the schematic level. The layout for these
    devices will be flattened by VXL when the layout-view is generated.
    There is no interest in creating a stdCell library for each of these
    cells so there is a one-to-one match that is LVS and reusable. The
    down side of this method is that you need to create each of these
    cells for every instantiation and the hiearchy is not completely
    maintained.

    Does anyone know of another approach to this methodology?
     
    rick, Aug 6, 2009
    #1
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