gate sizing and interconnect delay

Discussion in 'Cadence' started by mahalingamv, Jun 6, 2007.

  1. mahalingamv

    mahalingamv Guest

    hi all,

    why do most of the papers ignore interconnect delay when
    optimizing power/delay during gate sizing problem.

    is it something we can safely ignore even in circuits < 100 nm.

    thanks for the clarification.

    regards,
    Mali

    sorry if this is not a post directly related to this group.
     
    mahalingamv, Jun 6, 2007
    #1
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