gate-level simulation problem

Discussion in 'Cadence' started by Verictor, Feb 6, 2007.

  1. Verictor

    Verictor Guest

    Hi,

    I am running a gate-level simulation. The message is this:

    ncelab: *F, CUMSTS: Timescale directive missing on one or more modules

    I then ensured the message is for the library *.v file. I don't know
    if I need to specify the timescale in the library file. I really doubt
    if I need to do that since I am not suppose to touch it. Anyway, there
    seem other problems. When I tried to run the simulation no matter
    what, it gave me another error:

    Simulator "Design::" terminated abnormally. Use File->Open Simulation
    to open a connection to another simulator.

    What does that mean? RTL simulation works fine in this case.

    Thanks.
     
    Verictor, Feb 6, 2007
    #1
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