Flattening DEF Files

Dear SoC experts:

I have 12 DEF files representing a hierarchical design. I need to
flatten them into a single DEF file such that net and component
instance names are all correctly hierarchical.

I have heard this is possible using Cadence Encounter but have no clue
how to do it.

Can anyone please shed some light?

Thanks in advance.

HrH

 

It's been a while but you can probably do something like this:
import library.lef
import lowercellx.def
import lowercelly.def
....
import toplevel.def
export full.def

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com