Flat Verilog netlist - out

Discussion in 'Cadence' started by Rajeswaran M, Aug 11, 2004.

  1. Rajeswaran M

    Rajeswaran M Guest

    Is there a way to get flatten verilog netlist from a top level
    schematic, which has multiple hierarhies.
     
    Rajeswaran M, Aug 11, 2004
    #1
  2. Rajeswaran M

    Debbie Unger Guest

    Yes (do a search as it's been discussed before).
     
    Debbie Unger, Aug 27, 2004
    #2
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