Export layout from Encounter to VLE

Hi,

I am having some issues importing a layout into Virtuoso layout editor
from Encounter. First, I tried saving my layout as DEF in Encounter.
Then, I imported it using the "import DEF" option in design framework.
I believed I entered all the required information in the import menu
correctly.(such as the standard cell lib name and location etc.).
However, the layout I got in Virtuoso only contained interconnects.
All the cell instances are missing. Any suggestions on what might have
happened?

I also tried saving my layout in GDS format in Encounter. But the
StreamOut.Map file I have is not correctly matched to the technology I
am using. Therefore, the layout I got in Virtuoso has wrong layers.
My second question is if there is a way to automatically generate
StreamOut.Map file.

I am new to Encounter, your help will be highly appreciated.


ZW

 

Hi,
I am trying to develop the schematic to layout . I would like some
leads on how to create layout from the cells from the schematic.

supra

 

thanks for your reply ,

It is digital and analog but not semiconductor electronics. It is
superconducting electronics and cadence cells developed in my group
and both layout and schematic. So the netlist is a hierarchical
netlist.

 

Are you trying to do schematic driven layout? I am confused.
If you have the layout cells already, can't you just lay it out in
Virtuoso according to your schematic?

Can we stick to my problem in this thread?

 

yes I am trying to do a schematic driven layout. But i want to automate
it.

supra

 

I remember facing similar problems. I had not provided the reference
library names correctly. Once i modified them the layouts were visible
for standard cells. May be posting of the log file for the DEF in will
help to resolve the error quickly.

I have not tried Stream out from Encounter and hence will be unable to
comment on it.

Regards,
Mohan R

 

First, I tried saving my layout as DEF in Encounter.

This should work. If the cells are missing, then probably they could not be found. There should have
been errors reported in the CIW.

If you do have the standard cells layouts and you correctly inserted it in the reference libraries
field, then my only guess is that you do not have abstract views of the cells. To generate abstract
views, import the LEF containing the standard cells into cadence before importing your DEF.

It is very simple to create your own using information from your PDK.

Encounter does generate one automatically if you do not specify one, however it can not guess the
correct GDS layer numbers.

Furthermore, when streaming back the GDS into cadence, the layer map file (or stream layers from the
technology library) must match what was used when streaming out.


Stéphane

 

Hi mohanr,

Thanks for the reply. Below finds my CDS.log. I am not sure what
"cmos90site" is. I saw it in the floorplan menu but can't change it.
I did specify the correct name of the library when I import the DEF.

zhenning


\o CADENCE Design Systems, Inc.
\o
********************************************************************************
\o Loading IBM A&MS cmos9sf Procedures for Cadence Version "5.1.0"
\w *WARNING* techOpenTechFile: unable to open file techfile.cds in
library CMOS9SFRVT in r mode
\w *WARNING* property 'designRuleWidth' exists, ignored.
\w *WARNING* property 'FE_CORE_BOX_LL_X' exists, ignored.
\w *WARNING* property 'FE_CORE_BOX_UR_X' exists, ignored.
\w *WARNING* property 'FE_CORE_BOX_LL_Y' exists, ignored.
\w *WARNING* property 'FE_CORE_BOX_UR_Y' exists, ignored.
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\w *WARNING* Unable to find master cmos90site!
\o Processing VIAS Section
\w *WARNING* Layer 280 not found in DEF layer information.
\w *WARNING* Layer via1Array not found in DEF layer information.
\w *WARNING* Via 'via1Array_1' not found and no geometries are
described in VIAS section of the DEF file. May cause problems.
\w *WARNING* Layer 280 not found in DEF layer information.
\w *WARNING* Layer via1Array not found in DEF layer information.
\w *WARNING* Via 'via1Array_3' not found and no geometries are
described in VIAS section of the DEF file. May cause problems.
\w *WARNING* Layer 280 not found in DEF layer information.
\w *WARNING* Layer via1Array not found in DEF layer information.
\w *WARNING* Via 'via1Array_5' not found and no geometries are
described in VIAS section of the DEF file. May cause problems.
\w *WARNING* Layer 280 not found in DEF layer information.
\w *WARNING* Layer via1Array not found in DEF layer information.
\w *WARNING* Via 'via1Array_6' not found and no geometries are
described in VIAS section of the DEF file. May cause problems.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\w *WARNING* Unable to find site master cmos90site.
\o Processing COMPONENTS Section
\w *WARNING* Unable to find master INVX20VH!
\w *WARNING* Unable to find master INVX20VH. Instance clk__L2_I0 not
created.
\w *WARNING* Unable to find master INVX20VH!
\w *WARNING* Unable to find master INVX20VH. Instance clk__L1_I0 not
created.
\w *WARNING* Unable to find master DFFHQX8VH!
\w *WARNING* Unable to find master DFFHQX8VH. Instance position_reg[1]
not created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance data_reg[2] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance data_reg[3] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance data_reg[4] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance data_reg[5] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance data_reg[7] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_pb_reg[4] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_pb_reg[6] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_p_reg[4] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_p_reg[6] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Scm_p_reg[5] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Scm_p_reg[7] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_n_reg[4] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_n_reg[6] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Scm_n_reg[5] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Scm_n_reg[7] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_nb_reg[4] not
created.
\w *WARNING* Unable to find master EDFFX1VH!
\w *WARNING* Unable to find master EDFFX1VH. Instance Srf_nb_reg[6] not
created.
\w *WARNING* Unable to find master NAND2X4VH!
\w *WARNING* Unable to find master NAND2X4VH. Instance U126 not
created.
\w *WARNING* Unable to find master NAND4X2VH!
\w *WARNING* Unable to find master NAND4X2VH. Instance U127 not
created.
\w *WARNING* Unable to find master NAND2BX8VH!
\w *WARNING* Unable to find master NAND2BX8VH. Instance U128 not
created.
\w *WARNING* Unable to find master NAND2BX8VH!
\w *WARNING* Unable to find master NAND2BX8VH. Instance U129 not
created.
\w *WARNING* Unable to find master CLKINVX24VH!
\w *WARNING* Unable to find master CLKINVX24VH. Instance U130 not
created.
\w *WARNING* Unable to find master CLKNAND2X12VH!
\w *WARNING* Unable to find master CLKNAND2X12VH. Instance U131 not
created.
\w *WARNING* Unable to find master AND2X6VH!
\w *WARNING* Unable to find master AND2X6VH. Instance U133 not created.
\w *WARNING* Unable to find master INVX12VH!
\w *WARNING* Unable to find master INVX12VH. Instance U137 not created.
\w *WARNING* Unable to find master NOR2X8VH!

 

Hi Stephane,

Thanks very much for your help. You were correct. My standard lib
cells don't have abstract view. Follow you suggestion, I imported the
LEF before I import the DEF, now I do see all the cell instances in
Virtuoso. I guess I just need to do a search/replace now to change all
the abstract views to layout views.

However, I am having another problem. The vias Encounter uses
(V2_TOS_N, V3_H etc..) don't exist in my standard lib (see the CDS.log
below). The correct vias are located in another libary(other than the
libary that holds all the standard cells). Now all the vias are
missing in my imported layout. How do I let Encounter use the correct
vias?

Again, thanks very much for your help.

Zhenning


.......
\o Processing VIAS Section
\w *WARNING* Unable to find site master CMOS9SFRVT.
\w *WARNING* Unable to find site master CMOS9SFRVT.
\w *WARNING* Unable to find site master CMOS9SFRVT.
\w *WARNING* Unable to find site master CMOS9SFRVT.
\o Processing COMPONENTS Section
\o Processing PINS Section
\o Processing SPECIALNETS Section
.......
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V1S_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V3_H" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_V" for net clk__L2_N0 in via list.
\w *WARNING* Could not find VIA "V3_TOS_E" for net clk__L2_N0 in via
list.
\w *WARNING* Could not find VIA "V2_TOS_N" for net clk__L2_N0 in via
list.

 

I guess I just need to do a search/replace now to change all

Yes. Alternatively, in Virtuoso Preview there is the Floorplan/Replace View command.

If the vias exist in a separate library, but that library has been added to the reference libraries
for DEFin, I see no reason why it could not find them.

If you miss the vias in DFII, just import the technology part of the LEF (it is sometimes separate
from the cells themselves).

Or maybe this is a technology library issue, I'm not sure wether it looks for vias in the technology
library only or in the reference libraries. It it's the case, check that the techLibName attribute
of your standard cells lib points to the correct library.


If you really want Encounter to use different vias, that probably means you used the wrong
technology LEF when doing P & R.

cheers,

Stéphane

 

Hi Stephane,

I loaded two LEF files when I did Design Import to Encounter. One
contains macros for all the standard lib cells. The other one (see
below) defines RC values for timing driven routing, and it has all
wrong via names in it. I have to load it before I load the macro one
otherwise I will get an error saying:

**ERROR: (SOCLF-3): Error found when processing LEF file
'lef/cmos90_macros.lef'
**ERROR: (SOCLF-26): Seems no technology information defined in
fisrt lef file.
Please rearrange the lef file order and make sure the technology lef
file is the
first one, exit and restart First Encounter.
**ERROR: Load LEF file lef/cmos90_macros.lef failed

Any suggestions? Thanks for the help again.

Zhenning


cmos90_6lm_2thick_tech.lef
.........
LAYER M1
TYPE ROUTING ;
WIDTH 0.120 ;
AREA 0.07 ;
SPACING 0.120 ;
SPACING .18 RANGE 0.725 2.80 ;
SPACING .34 RANGE 2.805 8.00 ;
SPACING 1.02 RANGE 8.005 100000.0 ;
PITCH 0.280 ;
OFFSET 0.14 ;
DIRECTION HORIZONTAL ;
THICKNESS 0.2528 ;
HEIGHT 0.89 ;
MINENCLOSEDAREA 0.36 ;
MINIMUMCUT 2 WIDTH 0.72 ;
MINIMUMCUT 3 WIDTH 1.02 ;
MINIMUMCUT 4 WIDTH 2.10 ;
MAXWIDTH 25.00 ;
RESISTANCE RPERSQ 1.6940e-01 ;
CAPACITANCE CPERSQDIST 16.8556e-05 ;
EDGECAPACITANCE 7.2839e-05 ;
AntennaAreaRatio 298 ;
AntennaDiffAreaRatio 298 ;
END M1

LAYER V1
TYPE CUT ;
SPACING 0.18 ;
AntennaAreaRatio 10 ;
AntennaDiffAreaRatio 10 ;
END V1
.....

VIA V2_H DEFAULT
RESISTANCE 9.0000e+00 ;
LAYER M2 ;
RECT -0.07 -0.11 0.07 0.11 ;
LAYER V2 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER M3 ;
RECT -0.07 -0.07 0.07 0.07 ;
END V2_H

VIA V2_V DEFAULT
RESISTANCE 9.0000e+00 ;
LAYER M2 ;
RECT -0.11 -0.07 0.11 0.07 ;
LAYER V2 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER M3 ;
RECT -0.07 -0.07 0.07 0.07 ;
END V2_V

VIA V3_H DEFAULT
RESISTANCE 9.0000e+00 ;
LAYER M3 ;
RECT -0.13 -0.07 0.13 0.07 ;
LAYER V3 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER M4 ;
RECT -0.07 -0.07 0.07 0.07 ;
END V3_H

 

I loaded two LEF files when I did Design Import to Encounter. One

This is correct. You have to load first the technology LEF, which defines layers, vias etc...

If this is the LEF provided with your standard-cell library, I suspect that it is indeed the one you
should use.

If you would like to use other vias, then I'm questioning : where are they coming from ? Why don't
you use the provided vias ? Are they consistent with your technology ? Technically, it's very
possible to do, though. The reason I'm asking is, I feel like you are trying to have Encounter use
different vias which you already have in DFII for custom layout, instead of having the existing P&R
vias imported into DFII.

What I'm suggesting is : keep routing with the original LEF. However, import the technology part of
the LEF into Cadence Design Framework before importing the DEF file. Then, DEF import should go OK.

Stéphane

 

Hi Stephane,

Thanks very much for yesterday's help. I was not trying to use
different vias. The vias in the foundry provided LEF file are written
in the following format:

VIA V1_V DEFAULT
RESISTANCE 9.0000e+00 ;
LAYER M1 ;
RECT -0.11 -0.07 0.11 0.07 ;
LAYER V1 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER M2 ;
RECT -0.07 -0.07 0.07 0.07 ;
END V1_V

I assume there should be a cell called "V1_V" in my standard lib, but I
don't see any of them. Actually my standard cell ibrary doesn't
contain any vias cells, only digital gates and functional units. My
technology library (the one which holds all the mos, cap, resistor
symbols) has vias, but they are named differently from those in LEF(for
instance, viaM1_M2). Apparently, Encounter did the routing using vias
from the LEF file. But these vias can't be mapped to layout instances
in Virtuoso even I imported the LEF before I imported my DEF.

Is there another file which maps the LEF vias to Virtuoso vias? I
searched my PDK directory but didn't see anything. Do you have any
further suggestions?

Thanks very much in advance.


Zhenning

 

Ok. That's what I was expecting. You should not try to map the LEF vias to the vias existing in your
technology library. Instead, you should *import* the LEF file which contains the vias used for P&R
(the one you are giving an excerpt in your post). By doing this, all vias defined in the LEF, those
used for P&R, will be imported into your DFII library.

Remember that neither LEF nor DEF is a complete design, only the combination of the two. The LEF
part contains the technology/standard cells and the DEF file contains the netlist, placement and
routing, etc... Therefore, before importing a DEF file into DFII, the corresponding LEF should be
imported to generate the macros and technology-related cells that are referenced in the DEF.

Also, note that the vias in the LEF file are "optimized" for place & route (they are adapted to the
routing pitch, they include top-of-stack vias to satify minimum area requirements, possibly
double-cut vias for reliability, etc...) while the ones you already have in your technology library
are for custom-layout.

Stéphane

 

Hi Stephane,

I understand the concept much better now. Thanks for your explanation
about the differences between custom-layout vias and encounter vias.


I think I know what caused the missing vias now. When I imported the
two lef files (cmos90_6lm_2thick_tech.lef and cmos90_macros.lef) into
DFII, the first one (the one contains all the vias) failed. Therefore,
the vias were not imported. Do you know what might have caused the
failure in "LEF in"? (CDS.log below).

Thanks very much.

Zhenning



\w *WARNING* Via "V1_H" does not exist in the technology file
\e *Error* gec3LefInMain: Technology information different in the LEF
file and technology library "cmos9sf" not writable. LEFIN aborting...
\e
\e <<< Stack Trace >>>
\e (... in prtLEFInFormCB ...)
\e prtLEFInFormCB()
\e progn(prtLEFInFormCB())
\e hiFormDone(prtLEFInForm)
\e (... in hiDisplayForm ...)
\e (... in prtLEFInCB ...)
\e prtLEFInCB()
\e (... in hiDisplayForm ...)
\e (... in prtLEFInCB ...)
\e prtLEFInCB()
\e (... in hiDisplayForm ...)
\e (... in prtLEFInCB ...)
\e prtLEFInCB()
\r t
\r t

 

technology library "cmos9sf" not writable

Could this be the problem ?

What I usually do is create a new tech lib for a standard-cell library by copying the tech lib from
the design kit, possibly edit the technology file to remove unused devices, correct P&R attributes
etc., then import the technology LEF into it. Following, create a library to hold the standard cells
and associate it with this new tech lib, and import the LEF macros into it (they could also be
imported directly into the new tech lib itself, a matter of taste..).

Then, create a library to hold the designs, again associate it with the new tech lib, and import the
DEF designs into it.

Hope this will solve your problem.

Stéphane

 

What I usually do is create a new tech lib for a standard-cell library

Let me add one more thing : layer names may be different between the design kit's technology library
and the LEF technology file. This causes problems, because when importing LEF, layers are matched by
name and if they do not yet exist, new layers will be created. So, changing the layer names in the
cadence technology file to match those in the LEF is necessary.

Stéphane

 

Hi Stephane,

I followed your suggestions and was able to avoid the errors. It is a
good idea to create a new library to store all the cells and stuffs. I
think finally I am getting somewhere now. I appreciate your consistent
help very much. I wish you good luck on your research and work. Have
a good Christmas and happy new year in advance.

Best Regards,

Zhenning