Example of verilog-a serial bit source.

Hi. I was wondering if anyone has an example of a verilog-a bit
sequence source suitable for transient simulation. Basically, I have
an IC with a serial interface and want to simulate programming it with
an arbitrary (parameterized) bit sequence. The bit sequence will need
to be 128-bit depth. There is a SPI clock available to clock the
sequence.

I'm at home now, but when I get to work I will post what I have so
far.

Alternatively, if there is a spectre source which does the same thing,
that would work, too. I really don't want to go to a verilog module to
do this, since this would be the only digital block in my sim.

 

You can do this with a vsource in recent versions of spectre. Unfortunately
the choice does not yet exist in analogLib, but if you're putting the source
in an include file, it's perfectly possible to use it. Here's the solution
I wrote on this from sourcelink. The solution number is 11311934.

*Problem:


You want to create a voltage source representing a binary sequence - e.g.
101101101. You can do this with a piecewise linear source (e.g. vsource
with type=pwl), but this is rather cumbersome since you need to create
all the transitions.

Is there a simpler way to do this in spectre?

*Solution:


A new "bit" source type for vsource, isource, and port has been added
in MMSIM61.

NOTE: bit is currently not supported in vsource in analogLib. PCR 952356
has been filed for this issue.

The bit source has four states: "1", "0", "m" and "z", which represent the
high, low, middle voltage/current and high impedance state respectively.
It allows patterns defining a sequence of bits. It is also possible
to create pattern definitions which may be referenced by multiple sources.

Bit source parameters for sources
---------------------------------

The waveform parameters specify the characteristics of the waveform.

val1: High voltage/current value. This is the value for state "1".
val0: Low voltage/current value. This is the value for state "0".
delay: Delay time from the beginning of the transient interval to the
beginning of the first bit. It can be negative. The state in the
delay time is the same as the first state specified in data.
rise: The rise time from low value to high value.
fall: The fall time from high value to low value.
period: Length of a bit in second.

The Pattern parameters specify the sequence of the four states.

data: This is the bit string, which is a series of the four states, 1 0 m z.
In addition, this can also be a series of patterns and states.
Referenced pattern names can be defined with the pattern element
rptstart: The starting bit when repeating. Default value is 1. The data
repeats from the specified bit to the end of the bit string.
The value of the parameter should be an integer from 1 to the
length of the bit string.
rpttimes: The repeat times. Default value is 0. The parameter to set how many
times the specified bit string should be repeated. When its
value is -1, the string repeats forever. The output will maintain
the state of the last bit after the pattern has completed.

Parameters for pattern element
------------------------------

The pattern element supports the data, rptstart and rpttimes parameters
described above, with the exception that the rpttimes parameter cannot
be negative (i.e. you cannot define a pattern which repeats forever,
which is then referenced by a bit source).

Syntax and Examples of Bit Source
---------------------------------

Syntax for bit source:

Name ( p n ) vsource type=bit parameter=value ...

Syntax for pattern element:

pattern_name pattern parameter=value ...


Example of a simple bit source:

a0 ( a0 0 ) vsource type=bit val1=5 val0=0 delay=0 rise=1n fall=1n \
period=5n data="101mzzz10" rptstart=1 rpttimes=-1

Example of using defined patterns in bit source:

p1 pattern data="101m" rptstart=2 rpttimes=1
p2 pattern data="0z"
p3 pattern data="101" rpttimes=2

b0 ( b0 0 ) vsource type=bit val1=5 val0=0 delay=0 rise=1n fall=1n period=5n \
data="p1,p2,p3" rptstart=2 rpttimes=2

 

Funny that this question was asked three days after I had wasted 1 day
on looking at verilog-a to solve the problem and then found the
solution on sourcelink. I can confirm that the type=bit implementation
of vsource is the thing the OP is looking for. It works very nice if
it wasn't for the fact that it is not implemented in any analogLib
symbol, which I think should be done as quickly as possible as this
particular vsource implementation is solving a problem that engineers
have been struggling with since the pwl was invented. I guess the R&D
group is working high-priority on this, Andrew?

What really annoyed me was that verilog-a isn't able to handle arrays
in the same way as the OP is describing. It looks like Verilog-a is
not able to initialize vectors like integer data [1:64] =
"11011010100110101..." or something in that direction. Each index has
to be initialized on a separate assignment data[1] = 1; data[2] ="1";
etc. This looks like a weakness of verilog-a to me, but maybe it is
defined this way.

 

I chased the PCR to remind R&D. It's not the highest priority, but I've asked
for it to be considered for implementing soon.

Regards,

Andrew.

 

Well, once again, I read this post at home rather than at work. But,
anyway, what I recall is that an integer is actually defined as 32
bits, so you might be able to do something like integer data =
32'b00110011001100110011001100110011, although I haven't tried it.
However, either way it wasn't very convenient for something greater
than 32 bits.

 

Thanks for the info. Unfortunately, we are still on MMSIM60.