error in cadence mixed-signal simulation

Discussion in 'Cadence' started by Mekhail Anwar, Apr 23, 2005.

  1. Mekhail Anwar

    Mekhail Anwar Guest

    Hi
    I am getting an error message

    "*Error* length: argument must be a list or an array - "("\"Y\" \"A\"
    \"B\" \"VDD\" \"VSS\" \"VBULK\")"

    when i run the spectreSverilog simulator for mixed signal design. does
    anyone have any ideas as to the origin of this error? ... and what i
    can do to fix it?

    thanks,
    mekhail
     
    Mekhail Anwar, Apr 23, 2005
    #1
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