Encrypt schemtic

Is there any way to encrypt a schematic design, just like using
ncprotect to encrypt VHDL/Verilog, but still leaving VHDL/Verilog
accessible to simulation and LVS?

 

A schematic is equivalent to a netlist. If someone has a netlist
for which LVS is possible than he has everything and can
retreive the schematic.

I don't see a way where a netlist may be encrypted, except with
the ncprotect for digital simulation. LVS is not possible in this case.

2)
You may investigate on the VHDL or Verilog obfuscator tools.
If someone generates a schematic from such result, the obfuscation
will remain.

==================
Kholdoun TORKI
http://cmp.imag.fr
==================

 

With spectre you can encrypt a netlist (see the related chapter in the
manual), however it needs a separate licence apparently.

stéphane

 

That license was purely for auditing reasons due to import restrictions in
certain countries - it was not a cost option, by the way.

In recent ISRs the requirement for a license for this has been removed.

Regards,

Andrew.

 

I wish everyone did the same thing. For HSpice, Synopsys charges MORE
for the encryption license than the tool itself.

 

Thanks for the hint.
Does LVS work for such encrypted netlist ?
That's what the original post is asking.

==================
Kholdoun TORKI
http://cmp.imag.fr
==================

 

No. To be honest, it would be a bit pointless. The layout is more valuable
than the netlist - you could always extract a netlist from the layout, and
simulate that.

Similarly, encrypting the layout would be pointless, because you need to
manufacture it somehow...

Andrew.

 

Hi Andrew,

Encryption, compilation, or obfuscation, have different motivations
which all converge to protecting the IP sources. But the question
is : protecting for which purpose ?
When I look at the original post, I understand from the style
the motivation to protect a digital design, perhaps a hierarchical one.
(I may be wrong in my understanding ...)

The original message ask for encryption like ncprotect making
VHDL or Verilog simulation possible, *and* LVS possible.
And I translate the message with my understanding : making
impossible a retargetting with another standard-cell library to
another foundry etc ...
If someone has the source of the standard-cell netlist, and has
both the source library and the re-targetting library, it is quite
easy to recompile the design and optimize it for the new library
and migrate to a new foundry etc ...
That's what I understand from the original post.
One way to avoid such migration, is to flatten the netlist
at the transistor level, enabling the LVS to be possible,
and making migration quite impossible ...

For this particular request, I think the best thing to do, is to
produce the ncprotect netlist for simulation, and give an extracted
view or a flatten netlist until transistor level to make possible
the LVS.
Such transistor level netlist is enough criptic to make impossible
(or very hard) a retargetting or a reverse engineering.

2)
The idea of obfuscation is another way, and is useful also in
this case, since the standard-cell master name could also be
obfuscated.
The digital simulation library can be delivered with ncprotect,
and a CDL netlist library with the obfuscation which makes
very difficult the reverse engineering for each cell ...

Regards,

==================
Kholdoun TORKI
http://cmp.imag.fr
==================

 

Thanks all for your answers to my post. They made me know more clearly
what I need.