[Encounter] How to calculate clock frequency

Discussion in 'Cadence' started by Pasacco, Feb 10, 2008.

  1. Pasacco

    Pasacco Guest

    Dear

    As a newbie, my goal is to obtain clock frequency of the "core
    design", after routing, in SOC Encounter 6.2.

    My procedure was: Import -> Specify floorplaning -> Power ring and
    stripes -> Specify clock tree -> Place -> Route -> Timing optimize.

    When I tried to analyze timing, following result was obtained:

    +--------------------+---------+---------+---------+---------+---------
    +---------+
    | Setup mode | all | reg2reg | in2reg | reg2out |
    in2out | clkgate |
    +--------------------+---------+---------+---------+---------+---------
    +---------+
    | WNS (ns): | -0.244 | -0.244 | 1.329 | N/A | N/
    A | N/A |
    | TNS (ns): | -15.52 | -15.520 | 0.000 | N/A | N/
    A | N/A |
    | Violating Paths:| 208 | 208 | 0 | N/A |
    N/A | N/A |
    | All Paths: | 5016 | 2172 | 3288 | N/A | N/
    A | N/A |
    +--------------------+---------+---------+---------+---------+---------
    +---------+

    +--------------------+---------+---------+---------+---------+---------
    +---------+
    | Hold mode | all | reg2reg | in2reg | reg2out |
    in2out | clkgate |
    +--------------------+---------+---------+---------+---------+---------
    +---------+
    | WNS (ns): | -2.099 | -0.001 | -2.099 | N/A | N/
    A | N/A |
    | TNS (ns): | -5187.8 | -0.001 | -5187.8 | N/A | N/
    A | N/A |
    | Violating Paths:| 3097 | 1 | 3096 | N/A | N/
    A | N/A |
    | All Paths: | 5016 | 2172 | 3288 | N/A | N/
    A | N/A |
    +--------------------+---------+---------+---------+---------+---------
    +---------+

    My question is that :

    1. Can we derive the clock frequency from above?

    2. If yes, when clock period constraint = 2 ns, is following
    calculation correct?

    Clock frequency of core = 1/(2 + 0.244 + 0.001) = 444MHz.

    3. In summaryReport, following timing information is found.
    I do not understand why "#clocks in design = 0".
    Does this mean that "CTS" is not correct?

    Timing Information
    ---------------------------------------------------
    # Clocks in design = 0
    # Generated clocks = 0
    # "dont_use" cells from .libs = 67
    # "dont_touch" cells from .libs = 60
    # Cells in .lib with max_tran = 829
    # Cells in .lib with max_cap = 828
    # Cells in .lib with max_fanout = 0
     
    Pasacco, Feb 10, 2008
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.