DRC fix capability

Hi,

Does Cadence tool have DRC fixing capability?

Can anyone comment on that capability in Laker? Is it useful? Is it
hierarchical?

Thanks

 

Not sure what the DRC fixing capability is - but we do have a layout
optimisation capability (in VirtuosoXL) which can compact layouts as well as
solving many DRC errors - it can also de-compact to fix DRC errors.

Regards,

Andrew.

 

In addition to being part of product #3000 VirtuosoXL as Andrew stated,
the stated Virtuoso Layout Optimizer capability (which had its genesis
in the Cadence purchase of Q-Design Automation a few years ago, is also
now part of product #311 Virtuoso Layout Editor Turbo, at least in the
IC5141 time frame, if I remember correctly.

In addition, the NeoCell product line (which had its genesis in the
Cadence purchase of NeoLinear), can iteratively create layouts based on
schematic & constraint input, which, approaches the DRC problem in a
different manner.

Likewise, IC5141 Design Rule Driven Editing (DRD) approaches the DRC
challenge from yet another angle.

Hope this helps provide possibilities,

John Gianni
-- Nothing stated by me here is prior reviewed nor sanctioned by my
employer.

 

Not sure what you mean by fixing.

It is possible with DIVA ( and i am sure with ASSURA too ) to take the
output DRC markers and
turn them into new layout. I have used this capability when converting
a layout from one vendor to
another and have used it to do condtiional grows of specific sized
emitters in an analog technology.
(i.e. size the length only of 0.4ux5u EMI to 0.4ux6u while leaving
alone 0.5u wide EMI ... )

Careful use of the output layer in the internal DRC tools can fix
errors, but unless you are
very careful, you may not be able to revers the change.

One limitation is that DIVA flattens the data to the top level without
special care ...

YMMV ---

-- Gerry