DRAM circuits

hi everyone,

i teach a graduate vlsi class at UT austin, and there were a couple of
questions in my last lecture on DRAMs that i couldnt answer.

the text (weste and harris, "cmos vlsi design", 3rd edition, excellent
book) and my DRAM reference (keeth & baker, dram circuit design)
werent much help, so i thought i'd post the questions on the net.

- Q1. why is the bitline pre-charged to V_DD/2 (instead of V_DD). i
thought this would be for performance, i.e., get a larger swing
quicker, but at least from a simple model, the opposite seems to be
true. perhaps it's related to power or noise?

- Q2. shouldn't DRAM writes be faster than reads? (the logic being
that in reads, the bitline is driven by the trench capacitor, but in
writes the bitlinehas an active driver. perhaps the reason has
something to do with senseamp logic compensating for the slow read.)

looking forward to reading your replies,


cheers,
adnan

 

SWAG: back in the stone age of early DRAM arrays, some bits read 0 as a low
voltage and some as a high voltage. VDD/2 is smack in the middle so it's a
good place to precharge the bitline as it doesn't favor picking or dropping
bits.

How are you measuring read vs write operations? At the pins?

Unless you managed to write an entire row in one shot, every write is really a
read-modify-write operation...