Dracula LVS of S/D

Discussion in 'Cadence' started by madan.v.kumar, Jun 14, 2007.

  1. madan.v.kumar

    madan.v.kumar Guest

    We have folded/parallel transistors in our schematic. The shared
    nodes don't have contacts. When we run Dracula LVS we get errors that
    appear to indicate the S and D nets are swapped on the folded
    devices. Given the symmetry of the device, this error seems off.
    Assura doesn't flag this error!
    - Is there an option that one can set in Dracula that would check
    permutations of the pins?
    - Does Dracula have standard sequence in which it outputs the terminal
    of a FET (DGSB)?
    Thanks,
    mvk
     
    madan.v.kumar, Jun 14, 2007
    #1
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