Discipline Resolution

Discussion in 'Cadence' started by Stefan Joeres, Nov 22, 2006.

  1. Hi altogether,

    I do have a net labeled netA, connected to pinA and pinB (VerilogAMS
    building blocks).
    pinA and pin B can now be switched between electrical and logic
    implementation.

    The netA therefore can be either digital or analog.

    Now I'm tapping netA with a third pinC.

    Is there a way to have the pinC automatically detect whether netA is
    electrical or logic and have it behave in different manners ?

    The reason is that I don't want to have an connect module inserted between
    netA and pinC (would slow down simulation dramatically...).

    Regards,

    Stefan
     
    Stefan Joeres, Nov 22, 2006
    #1
  2. Hi Stefan,

    So is pinC within a Verilog-AMS model? You can of course choose to not
    specify the discipline, and thus it would resolve to whatever it is connected
    to. However, if it is a verilog-ams model, it presumably needs to do something
    with the net - and so would need to do different things in the code.

    So I don't think I can quite picture what you're trying to achieve here - I
    think you need to be a bit more explicit about your goals.

    Regards,

    Andrew.
     
    Andrew Beckett, Dec 3, 2006
    #2
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