difference between fingers and multiplicity in simulation

I am trying to get a definitive answer on the difference between the
fingers parameter and the multiplicity parameter in the cadence
symbols.

As I understand it, the spectre and spice simulation tools use
multiplicity to simulate devices in parallel. This then takes
advantage of the binning function in model files to more accurately
simulate devices. Rather than simulating a MOS device as a 20/2
device, you can simulate this as 10 2/2 devices if you design your
schematic with a 2/2 m=10 device. As a result you get a more accurate
simulation.

The question are as follows then.
1) Does spectre and/or spice simulate devices with m factors as
individual devices or does it assume that they are merged and share
common source/drain terminals to kind of estimate the reduction in
parasitics.
2) If a device is simulated as a single large device and broken up in
to smaller devices in layout, what kind of degredation could you
expect to see in performance. Is the degredation related purely to
parasitics?
3) How is the fingers parameter used in spectre simulation and how
does it differ from multiplicity?
4) Is the fingers parameter used in spice models?

Thanks,
Shawn

 

I do not think this is correct. The devices are quite different. First -
you'll have different parasitics and the other effect is that the first and
the last gate usually have different size because of the ununiform etching.

My oppinoin is would be best to simulate the same structure you're going to
put on the layout.

Depends on the model. I do not think it merges them. Easiest way to check -
compare 10 devices in parallel on the schematic with one that have
multipliciy 10.

More parasitics

You may eventually check the model

Probably

 

Shawn,

I understand that (when you neglect border effects) 10 MOSes of
width=2um in parrallel are the same as 1 MOS of with 20um , but what is
the advantage of making a split ?
I have seen splits in the length before, a channel is split in 4 MOSes
of length L/4 , and those "subMOSes" have drain and source areas of
zero, so that non-quasistatic effects are better modelled. But I have
never seen what you describe. How is it more accurate to split width, in
your experience ?

If I remember right, binning is some dirty trick in Berkeley MOS that
allows using different sets of model parameters in different "validity
domain". Kind of mixing compact modelling with lookup-table modelling
(yuck). If your models are binned and you want accurate results, you
could first look for non-binned models of those same devices (call the
foundry's spice modelling dept.).