Debugging Analog Errors while simulating VHDLAMS behavioral code using Cadence Spectre

Discussion in 'Cadence' started by badam.bs, Feb 27, 2007.

  1. badam.bs

    badam.bs Guest

    Hi

    Could you please help me out in debugging the analog Errors while
    simulating a VHDLAMS transistor level designs.

    The error from spectre looks like:

    "Error found by spectre during DC solution estimation, during IC
    analysis,
    during transient analysis `amsAnalysis'.
    Matrix is singular (detected at `tb_output' and `uInv.A1.irn').
    ncsim:*E, RNALER: simulation terminated due to analog error"

    I have no clue how to debug the Problem
    Thanks in advance. your help is awaited.

    --Srinivas
     
    badam.bs, Feb 27, 2007
    #1
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