Data base information for terminals

Discussion in 'Cadence' started by PolyPusher, Sep 23, 2009.

  1. PolyPusher

    PolyPusher Guest

    Hi all,

    I am trying to get the pin info for instances that are not in
    schematic and have no connectivity. For example, if you take a buffer
    that has connectivity and copy it on the layout canvas.

    If I select the buffer that has connectivity and type in the CIW:

    geGetSelectedSet(geGetEditCellView())~>instTerms~>name;i will get
    this...
    (("in" "vdd" "sub" "out"))

    for the buffer that I copied and have no connectivity I get

    geGetSelectedSet(geGetEditCellView())~>instTerms~>name;i will get
    this...
    (nil)

    I want to be able with skill to get the, I guess, lower level pin
    names for those instances without connectivity. I would think this
    is possible since if I select the buffer with no connectivity and
    leHiPropagateNets() it shows the lower level pins.......

    Any help would be appreciated,
    PolyPusher
     
    PolyPusher, Sep 23, 2009
    #1
  2. There is some confusion in your question, but if I guess correctly
    what you want the terminals names:

    geGetSelectedSet(geGetEditCellView())~>master~>terminals~>name

    and not the pins names, which you'd get with:

    geGetSelectedSet(geGetEditCellView())->master->terminals~>pins~>name

    Yours,
     
    Jean-Marc Bourguet, Sep 24, 2009
    #2
  3. PolyPusher

    PolyPusher Guest

    Sorry for the confusion, but you did answer my question.
    Thank you,
    Eric
     
    PolyPusher, Sep 24, 2009
    #3
  4. I forgot to explain what the confusion was.

    terminals and instTerms are logical objects used to represent the connectivity.

    one terminal can be implemeted by several pins (this is the weakconnect
    relationship), each pins can be implemeted by several figures (this is the
    strong connect relationship). The must connect relationship is represented
    by having several terminals flagged as having to be connect at the upper level.

    Yours,
     
    Jean-Marc Bourguet, Sep 24, 2009
    #4
  5. PolyPusher

    PolyPusher Guest

    I see how I confused the conversation. I had spent most of my career
    (10 of 12 years) at Intel and there lingo is different, for example a
    "Master" for Cadence is a "child" or "leaf" cell for Intel. Weak and
    must connect is handled by "ee class", which tells the tool and user
    if a net is connected in the "child" or not.

    Other funny things....a pin is a terminal on the "edge" of a child, a
    port is a terminal not on the "edge".

    Anyways, I really appreciate your help.
    PolyPusher
     
    PolyPusher, Sep 24, 2009
    #5
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