current through inherited connections

Discussion in 'Cadence' started by chava, Mar 7, 2006.

  1. chava

    chava Guest

    Hi,

    I have a circuit with sub-blocks whose VDD and GND are specified with
    inherited connections. I want to measure GND current from each of these
    blocks(not just the total). I do not know how to specify such a
    measurement in ADE or Ocean. Did anybody face this situation? Any help
    appreciated.

    Regards,
    chava.
     
    chava, Mar 7, 2006
    #1
  2. chava

    John Gianni Guest

    You can check to see if this express topick is covered in the updated
    Inherited Connections Tutorial.

    This Customer tutorial is available for download on Sourcelink,
    complete with a sample design kit with sample designs using inherited
    connections, multiple power and ground supplies, explicit and implicit
    inheritence, net expressions, etc.

    Here is the link for Cadence Customers.
    http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html

    Let us know if that serves your purpose or not.

    If it doesn't serve your purpose, request an update there's a feedback
    link or use the normal support process). The goal is to continue to
    improve that Cadence inherited connections tutorial to contain the
    working examples Customers really need to see.

    Good luck,
    John Gianni
     
    John Gianni, Mar 7, 2006
    #2
  3. chava

    John Gianni Guest

    Sorry for the typos in the prior posting (I was hurrying to a meeting
    and wanted to get you the answer).

    Here is what the Inherited Connections Tutorial covers.

    Inherited connections are an extension to the connectivity model that
    allow you to create signals hierarchically and to override their names
    for selected branches of a design hierarchy.

    This flexibility allows you to design:
    * Parameterized power and ground signals
    * Overridable substrate connections
    * Multiple power supplies for a design
    * Learn the difference between implicit and explicit inherited
    connections and when to use each
    * *New* Interaction with the verification environment (ASSURA LVS)
    or with parasitic resimulation
    * *New* Inherited Connection: DCME and Verilog-A

    Download the version 3.0 tutorial database and the "Virtuoso®
    Inherited Connections Flow Guide" manual to learn more about using
    inherited connections with Cadence tools. The manual contains
    illustrations and step-by-step instructions that show how inherited
    connections let you selectively override signals in designs created
    with the Virtuoso® Schematic Editor, and how those connections are
    available to other Cadence tools across the design flow.
     
    John Gianni, Mar 7, 2006
    #3
  4. There's a PCR enhancement for this:

    PCR: 397541
    Title: Would like to be able to select current through inh conn

    The only way to do it right now is to put save statements in an include file,
    referencing the terminal number of the hierarchical instance name, and then
    include that - you'd then have to look at the results via the results browser.

    Andrew.
     
    Andrew Beckett, Mar 20, 2006
    #4
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