Creating a real simulation model of a piece of wire

Hi,

this is probably a very easy question for you layouters out there:

I would like to create an av_extracted of a piece of wire for use in my
simulation testbench.

So far I have used simulation res and cap and calculated a lot of data
from the design manual. Then I thought it must be much easier to place a
piece of wire in the layout editor, extract that layout to av_extracted
and include that in my config view. That would have the great advantage
that I can easily change the length of the routing metal in order to see
what will happen with the rest of the system.

How would I do this?

Kind regards,

 

Hm, maybe I should consult the documentation to see if there is more
information on this as I am not in the position to pay bribes.

I placed a piece of metal 2, attached a shape pin in both ends, called
them sig_in and sig_out and then started rcx. It complained that it
wanted a netlist. Looks like RCX wants to make some kind of lvs before
it spits out capacitances and resistances.

Nah, this is really so simple that it has to be made complicated.

 

Lots of people want to run a detailed extract before they have a completed
circuit!
Typically you may have a particular signal (or pair or set) that you feel is
much more
sensitive to HF effects (say a virtual ground node on a op-amp or an input
diff pair signal to
your amp or a "quiet" reference signal or an "(oft repeated) buss structure)
The part of the circuit you are designing can sometimes be reduced to the
wire(s) of concern and
a few neighboring elements.

The layout of these structures may warrant the extremely accurate simulation
that you cannot do everywhere!



(note that LVS used to silently crash when fed a list of nodes but no active
elements! I always told
users that this was normal, but I was never sure!)


<Rant mode on>

One of my rants at Cadence (Ted.V et al) was that I wanted to be able to
"view"
devices at different abstraction levels. One that I asked for was the
concept of an
abstracted wire. The twisted logic goes something like this.

At the basic level a wire is just an ideal connection between different
devices. This ideal
connection had 0 delay, no charge capacity, no capacitance, no inductance,
no losses.
This is trivial to model in both the digital (state) domain and in the
analog (continuous) domain.
(This is essentially the model that almost always exists initially for a
wire)

I proposed another level (or levels) of views of a net where we could model
the layout more accurately
with deliberate subnets and model what we expect. This was proposed by
observing how parasitic resistance
was initially proposed to work
(i.e the concept was to break apart a net into subnets using some
terminology such as <NETNAME>.<SUBNET>
and that tools would be able to handle the concept that all
<NETNAME>.<SUBNETn>'s were part of the same net.
( i.e. LVS would see one<NETNAME> and make sure everything was connected,
and analog simulators could see
R (and the always promised L ) between sub-net components. This "view" of
a net would let us start to model a situation that is
closer to the reality that losssy interconnect has. This ability has been
hidden inside the tools that extract resistance
(and inductance) from the layout designer. Without internal Cadence
support, this concept died an early death.

<Rant mode off>


PS ... anyone going to CDN Live (not I)

-- Gerry Vandevalk