Create schematic from RCX extrated view

Discussion in 'Cadence' started by Tim, Feb 22, 2007.

  1. Tim

    Tim Guest

    Is there a way to create a schematic view from and RCX extracted view?

    The extracted is almost a schematic already but it would make probing
    easier if it could be converted into a real schematic view.

    I did find a answer about converting it to a Verilog view and then
    converting to a schematic view but I'm not sure that will work on my
    transistor level schematic.

    Thanks in Advance,
    Tim
     
    Tim, Feb 22, 2007
    #1
  2. Tim

    S. Badel Guest

    The extracted is almost a schematic already but it would make probing
    You can probe in an extracted view... in fact, i think it is much better, since in the extracted
    view you can easily find the nets you are looking for - they are where you have drawn them :)

    If you generate a schematic from the extracted view, all components will be placed randomly.

    If however you really want to do it, see below.
    This is just to "fool" the connectivity-to-schematic tool, which would not accept an extracted view
    as input because it's not an "eligible viewtype". Dont ask me why.

    Alternatively, copying the av_extracted view into a schematic view will do the trick, then you can
    run "Import->Netlist View" to place & route and get a working schematic.

    Below's some code to copy the extracted view to a schematic.


    Hope this answers you question.

    Stéphane



    procedure( ExtractedToSchematic( lib cell view @optional (destview "netlist") )

    let( ( lay sch schinst schterm netexpr )

    lay = dbOpenCellViewByType( lib cell view nil "r" nil )
    sch = dbOpenCellViewByType( lib cell destview "schematic" "w" nil )

    foreach( term lay~>terminals
    schterm = dbCreateTerm( dbMakeNet( sch term~>net~>name ) term~>name term~>direction )
    when( netexpr = dbGetTermNetExpr( term )
    dbCreateTermNetExpr( schterm netexpr )
    ) ; when
    ) ; foreach

    foreach( inst lay~>instances
    schinst = dbCopyFig( inst sch )
    foreach( instTerm inst~>instTerms
    dbCreateInstTerm( dbMakeNet( sch instTerm~>net~>name ) schinst dbFindTermByName(
    schinst~>master instTerm~>term~>name ) )
    ) ; foreach
    ) ; foreach

    dbClose( lay )
    dbSave( sch )
    dbClose( sch )

    ) ; let

    ) ; procedure
     
    S. Badel, Feb 22, 2007
    #2
  3. Tim

    Tim Guest

    Thanks Stephane!

    That worked great creating the netlist view.

    I have one problem during the Import >>> Netlist View. In the
    schematic view that is created the parasitic components from RCX come
    through from the correct library but the PDK components don't. They
    are all created in the schematic library. I tried listing the PDK
    library on the menu and removed the libraries that were there and it
    aborts. Any hints how to correct this would be greatly appreciated.

    Thanks Again,
    Tim
     
    Tim, Feb 23, 2007
    #3
  4. Tim

    Tim Guest

    Hi Stephane,

    I got the translation to work correctly. I opened the netlist view and
    did a search and replace of ViewName ivpcell and replace with symbol
    and now the symbols come through correctly on Import >>> Netlist View.

    This now gives us the capability to create schematics views of layouts
    which didn't have one. The schematic view of an RCX run can also now
    be modified for simulation.

    Thanks for your help,
    Tim
     
    Tim, Feb 23, 2007
    #4
  5. Tim

    S.Badel Guest

    For the record, using this trick I had a problem with inherited
    terminals.

    What happened is, the connectivity-to-schematic was inserting labels
    conflicting with the net expression... I found no way to prevent that,
    and fixed it by manually removing those labels.

    For example : a VDD pin with net expression [@VDD:%:vdd!]. The
    schematic pin is created with the net expression, but there's a label
    'VDD' on the wire, and the schematic extractor complains that net VDD
    is shorted to net vdd!

    Stéphane
     
    S.Badel, Feb 23, 2007
    #5
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