cosimulation

I am prototyping a IP core which was written in verilog languge in
cyclone II FPGA.My application engineer wrote code in C for
application level.Can i simulate the both in cadence simulation
environment so that i can find the bug in real environment .Can anyone
suggest on this.I am in desperate situation.Please help me.
Thanking you kumar

 

You didn't say which simulator you're trying to use. If it's ncsim (or
ncverilog), you can link in C code either via SystemC, or using
VPI (Verilog Programming Interface).

Regards,

Andrew.

 

I am using ncverilog compiler.How to use systemC.Can u provide
document or link for that .Please help me.Thanking you
VSRPKUMAR

 

This will be covered in the documentation for the IUS version you have. Access
it using "cdsdoc", or "cdnshelp" if you're using IUS61. The PDF files can also
be found under <IUSinstDir>/doc/ncsc* .

Andrew.