Corner Analysis

Hi,

I wanted to know what exactly do you mean by corner analysis and for a
given circuit how do you do it especially in cadence. If someone can
point me to a reference or a doc in cadence documentation I would be
grateful. Most importantly I need to understand what corner analysis
means even before I can learn how to do it in Cadence.

Thanks
Vaibhav

 

If I am right in understanding your question, then this is the answer:
Circuit design and performance depends on, among other things, process-
voltage-and-temperature (PVT) variations. Because of statistical
nature of IC fabrication, the device parameters (eg Vth, W, L of a
FETs, beta of BJTs etc.) vary from device to device, chip to chip.
However foundries provide the worst/typical/best case estimates of
such variations. You can check this in the model files. When you start
Analog Artist/Design Environment and load the device model files,
there is a "section" field which takes care of process variation -
given by 'tt', 'ss', 'ff' usually. tt means typical-typical for nFET
and pFET. 'ss' = slow-slow and ff for fast-fast. There are other
corners too like sf, fs, etc. They can be changed for each set of
simulation, or you can use ocean scripts to take care of them.

Then there is temperature corners. Depending on the needs, the circuit
may have to work from -40 C to 80 C or so. On top of these variations,
the circuit must still work if the supply changes, sy by +/- 10-20
percent.

Hope this answers.
-AJ

 

My opinion: Corner simulations are PVT, Monte-Carlo simulations are
statistical variations.
The process part of the PVT is, as you say, provided by the Foundry,
but that is not statistically, but empirically extracted from the
actual processing by adjusting the processing steps in such a way that
you deliberately introduce parameter skew. Example is modifying the
doping step so that you force VTHp to be at one extreme and VTHn at
another extreme. You will then get hh hl lh ll corners. (which are
maybe the sf fs ss anf ff corners). Important is that the PVT process
data are made to fit real wafer conditions.

The monte-carlo (or statistical) data tries to capture the different
kinds of variations in processing across wafer batches, across one
wafer, across one die. Monte-carlo is a mismatch simulation. If you
perform enough mc runs on a circuit, you will be able to extract the
process-sensitive circuit elements in your design. You will also be
able to see the variation of offset in differential stages which you
normally will not see when all transistors are the same. MC is
becoming more and more important as the geometries are shrinking. New
subjects like "Statistical Analog Design Methodologies" will be needed
by new engineers.

Or you use the corner tool which is a part of the Analog Design
Environment. Basic setup is not trivial, but if you get pcf and dcf
files from your foundry, it is probably the best place to start. You
cannot run monte-carlo on corners from this tool, and you cannot sweep
parameters (at least in versions prior to IC6. I don't know what
happens in later IC versions as it takes real long time for industry
to catch up with the latest movements from Cadence)

I would see the corner simulation as something that is defined by the
application in which the chip is going to work: What is the worst
possible condition? What is the best possible condition? What is a
"typical" condition? In a condition, voltage, temperature and process
is explicitly given as worst: (P=slow, V=Vnom+10%, T=125), best:
(P=fast, V=Vnom-10%, T=-40) typical: (P=nom, V=Vnom, T=50) The
temperature is normally the junction temperature and is for nominal
processes 27 degrees celsius, but realistic in a system is somewhere
around 40-70 degrees.