Converting synthesized VHDL/Verilog to spice netlist

Discussion in 'Cadence' started by Noohul Ali, Apr 21, 2005.

  1. Noohul Ali

    Noohul Ali Guest

    Dear All,
    I'm trying to get Spice netlist file from Verilog/VHDL. After I
    synthesized the vhdl file using Synplify, what tools available that
    can help me to get the spice netlist. I need the interconnect
    information incorporated in the spice netlist. Any help will be very
    useful
    Thanks,
    ali
     
    Noohul Ali, Apr 21, 2005
    #1
  2. Noohul Ali

    Neo Guest

    I think a backend layout tool would be able to do it. at least verilog
    to spice conversion is done by mentor tool.
     
    Neo, Apr 28, 2005
    #2
  3. Noohul Ali

    Neo Guest

    I think a backend layout tool would be able to do it. at least verilog
    to spice is done by mentors tool.
     
    Neo, Apr 28, 2005
    #3
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. How to convert VHDL/ verilog code to layout?

  2. Looking for top Verilog, VHDL reference texts?

  3. Top Verilog & VHDL reference books at over 50% off

  4. Bone up on VHDL & Verilog with these great reference texts at 60% off Amazon

  5. Verilog & VHDL reference texts

  6. Recommended reference books for VHDL & Verilog

  7. Books, books, books: best reference texts for Verilog and VHDL

  8. how to make Verilog netlist without a Verilog license

Loading...