Hi All, I am facing a typical problem of convergence. My aim is to find out the verification speedup for the Large AMS circuits by using behavioral models. To write the behavioral models , I have used Verilog-A code. I am using cadence spectreVerilog. But to my utter disappointment I found that the Convergence is the main culprit for the simulation speedup. Can any one suggest how to get rid of this problem? Is it advisable to choose some integration method in the Cadence ADE window like euler or trapezoidal or anything else? Please suggest as soon as possible. Thanking you, Yours sincerely, Debjit ====================== Debjit Pal MS Student and Research Consultant Department of Computer Science and Engineering IIT Kharagpur