connecting a wide wire net to gnd!/vdd!

I have to connect one bit of a bus (ie foo<7:0>) to ground, but if I
directly connect it to a ground symbol it gives an error saying that
net foo<0> is shorted to gnd!.. For simulation purposes I can use a 1
ohm resistor, but now I have to draw the layout for the schematic, and
that resistor gives a big headache.. What is the formal way to do the
connection? (problem is merely at the schematic level, for the layout
I can simply connect it by a Metal 1 path)..

 

One possible solution is to connect each wire from bus to ground.
That’s mean you should apply for example gnd<0:7>
Another solution is to terminate it to a wire, instead of instance.
Look "Understanding Connectivity and Naming Conventions" part of the
"schematic composer user’s guide".

 

If the bus is an internal net, you can use the "patch" component from analogLib,
which creates aliases in the database.

However, you cannot connect a pin to a global, or a global to a global, or a pin
to a pin, using patch. If you need to do that, you can use "cds_thru" in basic,
which will put a psuedo-short in - it needs some support in the verification
tool (it netlists in CDL as a small value resistor, which Dracula and Assura can
ignore if you set the *.RESI option in the netlist; in Diva you can add the
removeDevice() command to your LVS rules to short it out). In other tools
cds_thru is treated as either a current probe or a zero-voltage source, or a
short (in Verilog). It also has the lxRemoveDevice property on it so that
VirtuosoXL can treat it as a short too.

Note, patch doesn't need to go to these lengths, because it implements an
alias in the database which means that the nets are really shorted.

Regards,

Andrew.

 

Thank you very much.. "patch" sure solved my problem and thanks for
the info on "cds_thru"..
Regards,
Serkan Ozdemir