doesn anybody know any tricks for getting conformal to compare abort points? i have a simple cone of logic that doesn't seem complicated. i can pretty much "eyeball" it in the schematic viewer and verifiy its logicially equivalent myself. this is an rtl2gate run. i've tried a high effort compare on them and also tried a compare with the "flow partitioning". but have had zero success. i've run this design using formality and its finished no problem.
