config cellviews in Hierarchy Editor vs. VHDL configurations for AMS Designer i.e. ncsim

What is the general opinion/advice/solution on this setup:

Due to "strategic decisioning" Alice and Bob must work on different
workflows.

Bob uses plain ASCII to write VHDL that is compiled, elaborated and
simulated with ncsim.

Alice uses schematic (DFII) based design, and Hierarchy Editor´s AMS
Plug-In to configure, netlist, compile, elaborate and simulate.

Alice must deliver a DUT to Bob. This DUT must be configurable, i.e.:
Bob must be able to choose between different setups -provided by
Alice-
by using one of several VHDL configurations for his top level. This
top level is several
hierarchy levels above where he plans to insert Alice´s DUT.

Due to Alice´s workflow, she has got a schematic describing the
internal connectivity of the DUT (, plus a
symbol for it). She can use AMS Designer to netlist all her schematics
to Verilog-AMS, but finds no fun
at all in having to translate these Verilog-AMS netlists in VHDL-AMS
so that the VHDL configuration
mechanism can work on Bob´s side; neither Bob finds it funny..

Do you know of any way to make VHDL configurations and config
cellviews work together?
(?)

thanx.

(YAVEH-) Yet Another Verification Engineer Hoping-

 

This is a topic that interests me too. I see that you are using
Cadence only tools, ncsim, ams etc., so I would just call Cadence
Support and ask them what I should do. This is something that they
should know out of their heads as it is actually happening in about
any company dealing with analog and digital design: Analogs do
schematic, Digitals do text. If it is Verilog or VHDL is just a matter
of taste. Your company is probably paying a lot for support anyway, so
use it....

Config views and setup is a fragile construct with plenty of pitfalls
in Cadence, and the error messages you get is seldom related to the
real error as you pass through the wrapper layers.

 

Huh? Config views are pretty robust, so I'm not sure what all these pitfalls
you're talking about are.

As for the original question, I did write a sourcelink solution for getting VHDL
configurations and HED config views to play together - but it is quite
limited... I'll dig out the number when I'm back on line.

Regards,

Andrew.

 

The solution number is 11026432 which you can find on sourcelink. Note, this
approach does not work for AMS in ADE, only for AMS running within the hierarchy
editor plugin.

Regards,

Andrew.

 

The solution number is 11026432 which you can find on sourcelink.

Thanks for the link!

Unfortunately I don't know if I am allowed to publish your solution
here, so I can't ask for other interpretations.

My interpretation of your solution describes a case where Bob delivers
a digital sub-block for Alice to integrate in her analog top-level.
That is not my case here.

My case described Alice delivering to Bob (who don´t have DFII nor
Hierarchy Editor) a full mixed signal Design under Verification (DUV)
in the form of VHDL(-AMS) and/or Verilog(-AMS) plus "config
cellviews", so that Bob can integrate this source
code into his "only-ASCII" environment, instantiate this DUV in a VHDL
testbench, and use a VHDL configuration at the top to configure the
whole, down to the leaf cells, or "calling" any of the "config
cellvies"
provided by Alice.

I hope I could make the differences between the two cases clear.

regards,

(YAVEH-) Yet Another Verification Engineer Hoping-

 

That's clear. I'm not sure you can do that - but I've not tried.. If I have the
bandwidth, I'll see what I can do...

Regards,

Andrew.

 

Lots of magic happening in the background with possibility to override
with specific code. With experience, the config view is no problem,
but without .... When combining internal and external code like in the
example above, you have to know the limitations of config views (or
maybe more precise: The limitations of the current HED version)
_before_ you start the journey, otherwise you may have to redo things
a couple of times.