Compile verilog module-instances

Discussion in 'Cadence' started by Raf Karakiewicz, Feb 2, 2005.

  1. Raf Karakiewicz

    Raf Karakiewicz Guest

    Hi,

    I am running a spectreSverilog simulations and as long as my top-level
    verilog module contains no other module instances everything works fine.
    If now I add a module instance I get the following error during
    netlisting:

    Error! Module or primitive (inShiftReg) not defined


    I have an inShiftReg cellview with a functional view containing the
    verilog code. How do I make cadence compile all the modules together?

    Can anyone help me?


    Raf Karakiewicz
    Electrical Engineer
     
    Raf Karakiewicz, Feb 2, 2005
    #1
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