cdlout and pinMap option: why netlist is different ???

hello all,

i need your lights, once again.

I generated two different netlists using pinMap = 't and pinMap = 'nil
in my si.env file.

with option pinMap = 't, i have (sample):
XI29 PDZ N1 N0 PD
My problem is : N1 and N0 don't exist in my schematic !!


with option pinMap = 'nil, i have (sample):
XI29 PDZ VDD GND PD
This one is correct : my inverter is indeed connected to VDD and GND.

But, according to Cadence's docs: PinMap : Map Bus Name From <> to []
and i need to enable this option !

I really don't understand why option pinMap generates a kind of
"ghost" names.

Do you have idea please ?

Thanks a lot for your help.

Regards,

bu.

 

bu-bu wrote, on 12/04/08 01:39:

In Appendix C (auCdl Netlisting) of the "Virtuoso Analog Design Environment
User Guide" (in IC5141, at least) if you search for pinMap, it indicates that
other mapping is done when pinMap=t . For example, ! is mapped to nil. Any
mapping which goes to nil means that the name is invalid, and it will invent a
new netname. So, what this is saying is that nets with ! in (e.g. global nets)
will get completely renamed when pinMap=t - which is what you're seeing here.

The UI suggests that it is just mapping bus characters, but the mapping does
more than just bus characters, as this part of the documentation indicates.

This doc can also be found at <instdir>/doc/anasimhelp/anasimhelp.pdf

Regards,

Andrew.