CDLIN fails in translating resistors

Hi,

I'm seeking help for my CDLIN problems. I basically want to import a
CDL netlist containing two types of resistors into a virtuoso
schematic view. This is my (reduced) netlist:

..SUBCKT Rbias min nwell plus
*.PININFO min:I nwell:I plus:I
RR0 net13 min $SUB=nwell 5e3 $[r1] $W=440.00n $L=5u
**RR0 net13 min $SUB=nwell 5e3 $[RPPOLY] $W=440.00n $L=5u
..ENDS
..SUBCKT TOP A B
*.PININFO A:I B:O
RR1 VDDA vdda! 2.015m $[M3]
..ENDS

In the Rbias subcircuit I commented the original RR0 because I read on
Sourcelink that a model name shouldn't contain more than 2 characters.
Rbias is also instantiated in other subcircuits not shown here.
This is my device mapping file for CDLIN:

devMap := phyres RNPPO_MM
propMatch := subtype r1
termMap := PLUS PLUS MINUS MINUS SUB B

devMap := resistor RM3_MM
propMatch := subtype M3

I allocated termMap to the first resistor because my destination
device (RNPPO_MM in the technology library) takes terminal name B
instead of SUB. I guess termMap isn't needed for the second (2-pin)
resistor...?

Now, for this elementary case, I get a file ni.err saying:

PROCESSING INPUT FILE: tempNetlist.cdl
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT Rbias
** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE
THREE CHARACTERS ONLY
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT TOP

FILE :tempNetlist.cdl
*** NUMBER OF ELEMENT BOXES DEFINED : 2

and ni.log saying:

2 subckt(s) found in the netlist file.


==========================
Subckt: TOP
==========================

Created the CV TOP->netlist_tmp.
ERROR (CDLIN-44): The sub-circuit 'TOP' does not have any instance
(box element). Hence, its
schematic view will not be prepared.

Usage error.
Netlist.cdl INPUT

ENCOUNTERED 0 ERRORS ( 3 WARNINGS) DURING FILE INPUT

FILE :tempNetlist.cdl
*** NUMBER OF ELEMENT BOXES DEFINED : 2

CIRCUIT FILE INPUT AND PROCESSED


Can anyone help me on the definition of "box name" (is it the same as
saying "subcircuit name"?) or the fact that none of my two resistors
are identified with the current devMap.cdl file?

When I define, for example, a dummy transistor in the Rbias subcircuit
and adapt the devMap.cdl file accordingly, the tool sees a non-empty
subcircuit and only translates the transistor into the schematic.
Renaming Rbias to Kbias (assuming this is the "box name" not being
allowed to start with character R) doesn't help either.

Tips are much appreciated!
Regards,
Gerd

PS. I'm running icfb 5.1.41-USR5

 

The solution was: add *.BIPOLAR and *.CAPVAL to the CDL netlist
(otherwise analog passives are simply ignored)

Gerd