CBR file to drawn schematic

Hello,

I have a situation where I have a CBR file but not drawn schematic, is
there any way to produce a drawn schematic(ugly is fine, the design is
simple) from the CBR file?

Thank you,
Eric

 

PolyPusher wrote, on 04/21/10 14:25:

What's a CBR file?

Regards,

Andrew.

 

Hi,

It is the file that Calibre uses to compare "schematic"(CBR) against
layout. Example follows.

Thank you!
Eric

* RSS DFII to Calibre netlister output for RX0000_1
* Date of RX0000_1 netlist generation: 2010/04/01_10:53:25
* initialization file R:\rds\prod\HOTCODE\adslibs/de/bin/
cbrphemt7ap.ini used
..global 0
..subckt twvphemt t b
..ends
..subckt ind_p pos neg
..ends ind_p
..subckt lint pos neg
..ends lint
..subckt diode pos neg
..ends diode
..subckt fet_sg d g s
..ends fet_sg
..subckt fet_dg d g1 g2 s
..ends fet_dg
..subckt fet_tg d g1 g2 g3 s
..ends fet_tg
..subckt fet_4g d g1 g2 g3 g4 s
..ends fet_4g
..subckt fet_5g d g1 g2 g3 g4 g5 s
..ends fet_5g
..subckt fet_6g d g1 g2 g3 g4 g5 g6 s
..ends fet_6g
..subckt fet_7g d g1 g2 g3 g4 g5 g6 g7 s
..ends fet_7g
..subckt fet_8g d g1 g2 g3 g4 g5 g6 g7 g8 s
..ends fet_8g
..subckt fet_9g d g1 g2 g3 g4 g5 g6 g7 g8 g9 s
..ends fet_9g
..subckt fet_10g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 s
..ends fet_10g
..subckt fet_11g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 s
..ends fet_11g
..subckt fet_12g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 s
..ends fet_12g
..subckt fet_13g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 s
..ends fet_13g
..subckt fet_14g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 s
..ends fet_14g
..subckt fet_15g d g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 s
..ends fet_15g
..subckt fetln d g s
..ends fetln
..subckt fetln2 d g s
..ends fetln2
..SUBCKT __RX0000_1 sh_gnd2 V_series V_shunt sh_gnd1 Pin Pout
R45 _net1715 _net1674 $[res_bulk] w=3.200u l=75.300u r=Rgate
R31 _net1706 _net1677 $[res_bulk] w=3.200u l=75.300u r=Rgate
C11 _net1725 _net1714 $[CAP_MIM] Cff*1e-12
C1 sh_gnd1 _net1721 $[CAP_MIM] 3p
R30 _net1671 V_shunt $[res_bulk] w=3.200u l=0.000198 r=Rbias
R32 _net1705 _net1677 $[res_bulk] w=3.200u l=75.300u r=Rgate
R41 _net1668 V_shunt $[res_bulk] w=3.200u l=0.000198 r=Rbias
C8 _net1716 _net1705 $[CAP_MIM] Cff*1e-12
R38 _net1670 _net1668 $[res_bulk] w=3.200u l=75.300u r=Rgate
C2 sh_gnd2 _net1725 $[CAP_MIM] 8p
R4 _net1689 _net1697 $[res_bulk] w=3.200u l=0.000247 r=Rlin
R54 Pin _net1643 $[res_bulk] w=3.200u l=0.000198 r=Rlin
C4 _net1673 _net1643 $[CAP_MIM] Cff*1e-12
C10 _net1670 _net1721 $[CAP_MIM] Cff*1e-12
R39 _net1527 _net1668 $[res_bulk] w=3.200u l=75.300u r=Rgate
R36 _net1694 _net1697 $[res_bulk] w=3.200u l=0.000247 r=Rlin
xFET6 Pin _net1640 _net1447 _net1673 _net1643 FET_TG w=(1000)*1e-6
l=0.4u
xFET10 Pin _net1689 _net1694 _net1698 Pout FET_TG w=(1000)*1e-6 l=0.4u
R33 _net1707 _net1677 $[res_bulk] w=3.200u l=75.300u r=Rgate
C9 _net1644 _net1643 $[CAP_MIM] Cff*1e-12
R35 _net1677 V_shunt $[res_bulk] w=3.200u l=0.000198 r=Rbias
C12 _net1716 _net1715 $[CAP_MIM] Cff*1e-12
R42 _net1674 V_shunt $[res_bulk] w=3.200u l=0.000198 r=Rbias
xFET11 _net1643 _net1644 _net1527 _net1670 _net1721 FET_TG
w=(1000)*1e-6 l=0.4u
xFET12 _net1716 _net1715 _net1710 _net1714 _net1725 FET_TG
w=(1500)*1e-6 l=0.4u
R58 _net1716 _net1725 $[res_bulk] w=3.200u l=0.000198 r=Rlin
R37 _net1698 _net1697 $[res_bulk] w=3.200u l=0.000247 r=Rlin
R55 _net1643 _net1721 $[res_bulk] w=3.200u l=0.000198 r=Rlin
R27 _net1673 _net1671 $[res_bulk] w=3.200u l=75.300u r=Rgate
R29 _net1640 _net1671 $[res_bulk] w=3.200u l=75.300u r=Rgate
C7 Pout _net1706 $[CAP_MIM] Cff*1e-12
R28 _net1447 _net1671 $[res_bulk] w=3.200u l=75.300u r=Rgate
R43 _net1710 _net1674 $[res_bulk] w=3.200u l=75.300u r=Rgate
R40 _net1644 _net1668 $[res_bulk] w=3.200u l=75.300u r=Rgate
xFET7 Pout _net1706 _net1707 _net1705 _net1716 FET_TG w=(1500)*1e-6
l=0.4u
C3 _net1640 Pin $[CAP_MIM] Cff*1e-12
R44 _net1714 _net1674 $[res_bulk] w=3.200u l=75.300u r=Rgate
R59 Pout _net1716 $[res_bulk] w=3.200u l=0.000198 r=Rlin
R8 _net1697 V_series $[res_bulk] w=3.200u l=0.000198 r=Rbias
..ENDS __RX0000_1

..SUBCKT RX0000_1 Pin Pout V_series V_shunt sh_gnd1 sh_gnd2
X1 sh_gnd2 V_series V_shunt sh_gnd1 Pin Pout __RX0000_1 Rlin=20000
Rgate=5000
+ Cff=1.2 Rbias=15000
..ENDS RX0000_1

 

PolyPusher wrote, on 04/22/10 21:30:

Eric,

That looks like CDL (a format originally used by Dracula, which is heavily based
on SPICE).

There's File->Import->CDL you could use (or in IC61X, File->Import->SPICE). The
IC61 version is generally better - the parser's better, and also it can produce
better schematics. However, with a bit of work you can get the IC5141 import to
do useful things nevertheless. I think it's covered in the Design Data
Translator's manual (<instDir>/doc/transref/transref.pdf)

Regards,

Andrew.

 

Andrew,

I think I can get it to work, I have some homework to do.

Thanks again Andrew,
Eric