Capacitor Issue

Discussion in 'Cadence' started by hillbrk, Apr 7, 2006.

  1. hillbrk

    hillbrk Guest

    Has anyone used a capacitor in layout? If so, is there any way that the
    lvs will pass recognizing the cap in both the schmatic and layout?

    Thanks
     
    hillbrk, Apr 7, 2006
    #1
  2. hillbrk

    hillbrk Guest

    I am using AMIS C5 process
     
    hillbrk, Apr 7, 2006
    #2
  3. hillbrk

    Andrew Beckett Guest

    What a ridiculous question!

    Of course people have used capacitors in layout, and of course LVS can pass with
    capacitors in schematic and layout.

    Presumably you have a specific problem.

    You should realise that unless you post a reasonable question, with sufficient
    details, you cannot expect to get a reasonable answer.

    Regards,

    Andrew.
     
    Andrew Beckett, Apr 12, 2006
    #3
  4. hillbrk

    fogh Guest

    Andrew,

    agree on the lack of details. But... he gives already the details
    about the process/pdk and you would (still, maybe) be amazed how many
    obvious flow errors make it in a final pdk that is allegedly used all
    over the world and been around.
     
    fogh, Apr 13, 2006
    #4
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